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copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com ps024410-0108 preliminary product specification crimzon ? infrared microcontrollers zlp12840 otp mcu with learning amplification
ps024410-0108 p r e l i m i n a r y do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology describe d is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crim zon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
ps024410-0108 p r e l i m i n a r y revision history zlp12840 otp mcu product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page no january 2008 10 updated table 61 . 129 september 2007 09 updated features section, figure 2 , figure 3 , smr1 register events , and ordering information section. added applications and support tools section. 1 , 5 , 8 , 103 , and 141 july 2007 08 updated disclaimer page and implemented style guide. all february 2007 07 updated voltage detection section. 97 january 2006 06 removed the trademark symbol (tm) from lxm. all
ps024410-0108 p r e l i m i n a r y table of contents zlp12840 otp mcu product specification iv table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 i/o port pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 comparator inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 comparator outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 port configuration register (pcon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 port 0 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 port 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 port 2 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 port 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 port 3 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 port 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 memory and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 otp program/constant memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 register pointer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 linear memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 program memory paging register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 register pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 user data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 stack pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 register file summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 infrared learning amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . 45 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ps024410-0108 p r e l i m i n a r y table of contents zlp12840 otp mcu product specification v transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . 47 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . . 48 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . 49 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . . . . 49 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 uart receive data register/uart transmit data register . . . . . . . . . . . . . . 54 uart status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 uart control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 baud rate generator constant register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 t8 transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 t8 demodulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 t16 transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 t16 demodulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ping-pong mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 timer output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 counter/timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 timer 8 capture high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 timer 8 capture low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 timer 16 capture high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 timer 16 capture low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 counter/timer 16 high hold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 counter/timer 16 low hold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 counter/timer 8 high hold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 counter/timer 8 low hold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 counter/timer 8 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 t8 and t16 common functions register . . . . . . . . . . . . . . . . . . . . . . . . . . 78 timer 16 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 timer 8/timer 16 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 interrupt priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 interrupt request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 crystal 1 oscillator pin (xtal1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ps024410-0108 p r e l i m i n a r y table of contents zlp12840 otp mcu product specification vi crystal 2 oscillator pin (xtal2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 internal clock signals (sclk and tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 resets and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 power-on reset timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 reset/stop mode recovery status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 voltage brownout/standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 fast stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 stop mode recovery interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 stop mode recovery event sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 smr register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 smr1 register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 smr2 register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 smr3 register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 stop mode recovery register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 z8 lxm cpu programming summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 addressing notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 z8 lxm cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 applications and support tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ps024410-0108 p r e l i m i n a r y architectural overview zlp12840 otp mcu product specification 1 architectural overview zilog?s zlp12840 one-time-programmable (otp) mcu is a member of the crimzon ? family of infrared microcontrolle rs. it provides a directly-com patible code upgrade path to other crimzon mcus, offers a robust learning function, and features up to 128 kb otp read-only memory (rom) and 1004 bytes of general-purpose random access memory (ram). two timers allow the generation of complex signals while performing other counting operations. a uart allows the zlp12840 mcu to be a slave/master database chip. when the uart is not in use, the baud ra te generator can be used as a third timer. enhanced stop mode recove ry (smr) features allow the zlp12840 mcu to awaken from stop mode on any change of logic, and on any combination of the 12 smr inputs. the smr source can also be us ed as an interrupt source. many high-end remote control units offer a learning function. simply stated, a learning function allows a replacement re mote unit to learn most infra red signals from the original remote unit and regenerate the signal. however, the amplifying circuits of many learning remotes are expensive, are not tuned well. zlp12840 mcu is the first chip dedicated to solve this problem because it offers a built-in tuned amplification circuit in a wide range of positions and battery voltages . the only external componen t required is a photodiode. the zlp12840 mcu greatly redu ces system cost, yet improves learning function reliability. with all new features, the zlp1 2840 mcu is excellent for infrared remote control and other mcu applications. features table 1 lists the memory, input/output (i/o), and power features of the zlp12840 one- time-programmable microcontroller. the zlp12840 mcu supp orts 20 interrupt sources with 6 interrupt vectors that are listed below: ? two from t8, t16 time-out and capture ? three from uart tx, uart rx, uart brg table 1. zlp12840 otp mcu features device otp rom (kb) ram* (bytes) i/o lines voltage range zlp12840 mcu 32, 64, 96, 128 1004 24 or 16 2.0?3.6 v *general-purpose registers implem ented as random access memory.
ps024410-0108 p r e l i m i n a r y architectural overview zlp12840 otp mcu product specification 2 ? one from lvd ? 14 from smr source p20-p27, p30-p33, p00, p07 ? any change of logic from p20-p27, p30-p33 can generate an interrupt or smr additional features include: ? ir learning amplifier ? low power consumption?11 mw (typical) ? three standby modes: ? stop?2 a (typical) ? halt?0.8 ma (typical) ? low-voltage reset ? intelligent counter/timer architecture to automate generation or reception and demodulation of complex wave form and pulsed signals: ? one programmable 8-bit counter/timer wi th two capture registers and two load registers ? one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair ? programmable input glitch filter for pulse reception ? the uart baud rate generator can be used as another 8-bit timer when the uart is not in use ? six priority interrupts ? three external/uart interrupts ? two assigned to counter/timers ? one low-voltage detection interrupt ? 8-bit uart ? r x , t x interrupts ? 4800, 9600, 19200 and 38400 baud rates ? parity odd/even/none ? stop bits 1/2 ? low-voltage detection and hi gh-voltage detection flags ? programmable watchdog timer/power-on reset circuits ? two on-board analog comparators with independent reference voltages and programmable interrupt polarity ? one-time programmable eprom option bits (on/off) ? port 0 pins 0?3 pull-up transistors ? port 0 pins 4?7 pull-up transistors
ps024410-0108 p r e l i m i n a r y architectural overview zlp12840 otp mcu product specification 3 ? port 2 pins 0?7 pull-up transistors ? eprom protection ? watchdog timer enabled at power-on reset all signals with an overline, ? ?, are active low. for example, b/w , in which word is active low, and b /w, in which byte is active low. power connections use the conven tional descriptions listed in table 2 . functional block diagram figure 1 displays the functional blocks of the zlp12840 microcontroller. table 2. power connections connection circuit device power v cc v dd ground gnd v ss figure 1. zlp12840 mcu functional block diagram note: uart and 2 comparators watchdog timer brg timer counter/timers 8-bit/16-bit high/low power-on ir learning z8 lxm core register file banks 0?3 4 x 256 x 8 register file banks d & f 2 x 16 x 8 voltage detect reset amplifier register/peripheral bus p30/pref1 up to 128k x 8 bus otp and
ps024410-0108 p r e l i m i n a r y architectural overview zlp12840 otp mcu product specification 4
ps024410-0108 p r e l i m i n a r y pin description zlp12840 otp mcu product specification 5 pin description figure 2 displays the pin configuration of the zlp 12840 device in the 20-pin pdip, soic, and ssop packages. table 3 describes the functions and signal directio ns of each pin within the 20-pin pdip, soic, and ssop packages sequentially by pin. figure 2. zlp12840 mcu 20-pin pdip/soic/ssop pin configuration table 3. zlp12840 mcu 20-pin pdip/soic/ssop sequential pin identification pin no symbol function direction 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply 6 xtal2 crystal oscillator output 7 xtal1 crystal oscillator input 8 p31 port 3, bit 1 input 9 p32 port 3, bit 2 input 10 p33 port 3, bit 3 input 11 p34 port 3, bit 4 output 12 p36 port 3, bit 6 output p25 p26 p27 p07 v dd xtal2 xtal1 p31 p32 p33 p24 p23 p22 p21 p20 v ss p01 p00/pref1/p30 p36 p34 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin pdip soic ssop
ps024410-0108 p r e l i m i n a r y pin description zlp12840 otp mcu product specification 6 13 1 p00 port 0, bit 0 input/output p30 port 3, bit 0 input 14 p01 port 0, bit 1 input/output 15 v ss ground 16 p20 port 2, bit 0 input/output 17 p21 port 2, bit 1 input/output 18 p22 port 2, bit 2 input/output 19 p23 port 2, bit 3 input/output 20 p24 port 2, bit 4 input/output 1 when the port 0 high-nibble pull-up option is enabled and the p30 input is low, current flows through the pull-up to ground. table 3. zlp12840 mcu 20-pin pdip/soic/ssop sequential pin identification (continued) pin no symbol function direction
ps024410-0108 p r e l i m i n a r y pin description zlp12840 otp mcu product specification 7 table 4 describes the functions and signal directio n of each pin within the 20-pin pdip, soic, and ssop packages by function. table 4. zlp12840 mcu 20-pin pdip/soic/ssop functional pin identification pin no symbol function direction 13 1 p00 port 0, bit 0 input/output p30 port 3, bit 0 input 14 p01 port 0, bit 1 input/output 4 p07 port 0, bit 7 input/output 16 p20 port 2, bit 0 input/output 17 p21 port 2, bit 1 input/output 18 p22 port 2, bit 2 input/output 19 p23 port 2, bit 3 input/output 20 p24 port 2, bit 4 input/output 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 8 p31 port 3, bit 1 input 9 p32 port 3, bit 2 input 10 p33 port 3, bit 3 input 11 p34 port 3, bit 4 output 12 p36 port 3, bit 6 output 5v dd power supply 15 v ss ground 7 xtal1 crystal oscillator input 6 xtal2 crystal oscillator output 1 when the port 0 high-nibble pull-up option is enabled and the p30 input is low, current flows through the pull-up to ground.
ps024410-0108 p r e l i m i n a r y pin description zlp12840 otp mcu product specification 8 figure 3 displays the pin configuration of the zlp 12840 device in the 28-pin pdip, soic, and ssop packages. figure 3. zlp12840 mcu 28-pin pdip/soic/ssop pin configuration p24 p23 p22 p21 p20 p03 v ss p02 p01 p00 pref1/p30 p36 p37 p35 p25 p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31 p32 p33 p34 1 28-pin pdip soic ssop 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
ps024410-0108 p r e l i m i n a r y pin description zlp12840 otp mcu product specification 9 table 5 describes the functions and signal directio ns of each pin within the 28-pin pdip, soic, and ssop packages sequentially by pin. table 5. zlp12840 mcu 28-pin pdip/soic/ssop sequential pin identification pin symbol function direction 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 4 p04 port 0, bit 4 input/output 5 p05 port 0, bit 5 input/output 6 p06 port 0, bit 6 input/output 7 p07 port 0, bit 7 input/output 8v dd power supply 9 xtal2 crystal oscillator output 10 xtal1 crystal oscillator input 11 p31 port 3, bit 1 input 12 p32 port 3, bit 2 input 13 p33 port 3, bit 3 input 14 p34 port 3, bit 4 output 15 p35 port 3, bit 5 output 16 p37 port 3, bit 7 output 17 p36 port 3, bit 6 output 18 p30 port 3, bit 0; connect to v cc if not used input 19 p00 port 0, bit 0 input/output 20 p01 port 0, bit 1 input/output 21 p02 port 0, bit 2 input/output 22 v ss ground 23 p03 port 0, bit 3 input/output 24 p20 port 2, bit 0 input/output 25 p21 port 2, bit 1 input/output 26 p22 port 2, bit 2 input/output 27 p23 port 2, bit 3 input/output 28 p24 port 2, bit 4 input/output
ps024410-0108 p r e l i m i n a r y pin description zlp12840 otp mcu product specification 10 table 6 describes the functions and signal directio ns of each pin within the 28-pin pdip, soic, and ssop packages by function. table 6. zlp12840 mcu 28-pin pdip/soic/ssop functional pin identification pin symbol function direction 19 p00 port 0, bit 0 input/output 20 p01 port 0, bit 1 input/output 21 p02 port 0, bit 2 input/output 23 p03 port 0, bit 3 input/output 4 p04 port 0, bit 4 input/output 5 p05 port 0, bit 5 input/output 6 p06 port 0, bit 6 input/output 7 p07 port 0, bit 7 input/output 24 p20 port 2, bit 0 input/output 25 p21 port 2, bit 1 input/output 26 p22 port 2, bit 2 input/output 27 p23 port 2, bit 3 input/output 28 p24 port 2, bit 4 input/output 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 18 p30 port 3, bit 0; connect to v cc if not used input 11 p31 port 3, bit 1 input 12 p32 port 3, bit 2 input 13 p33 port 3, bit 3 input 14 p34 port 3, bit 4 output 15 p35 port 3, bit 5 output 17 p36 port 3, bit 6 output 16 p37 port 3, bit 7 output 8v dd power supply 22 v ss ground 10 xtal1 crystal oscillator input 9 xtal2 crystal oscillator output
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 11 i/o port pin functions the zlp12840 mcu features three 8-bit ports, which are described below. ? port 0 is nibble-programmabl e as either input or output ? port 2 is bit-programmable as either input or output ? port 3 features four inputs on the lower nibble and four outputs on the upper nibble port 0 and 2 internal pull-ups are disabled on any pin or group of pins when programmed into output mode. the cmos input buffer for each port 0 or 2 pin is always connected to the pin, even when the pin is configured as an output. if the pin is configured as an open-drain output and no external signal is applied, a high output state can cause the cmos input buffer to float. this might lead to excessive leakage current of more than 100 a. to prevent this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is low, especially during stop mode. port 0, 1, and 2 have both input and output capability. the input logic is always present no matter whether the port is configured as input or output. when doing a read in- struction, the mcu reads the actual value at the input logic but not from the output buff- er. in addition, the instructions of or, and, and xor have the read-modify-write sequence. the mcu first reads the port, and then modifies the valu e and load back to the port. precaution must be taken if the port is configur ed as open-drain outp ut or if the port is driving any circuit that makes the voltage d ifferent from the desired output logic. for example, pins p00?p07 are not connected to an ything else. if it is configured as open- drain output with output logic as one, it is a floating port and reads back as zero. the following instruction sets p00-p07 all low. and p0,#%f0 table 7 summarizes the registers used to contro l i/o ports. some port pin functions can also be affected by control registers for other peripheral functions. note: caution:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 12 port 0 port 0 is an 8-bit, bidirectional, cmos-com patible port. its eight i/o lines are configured under software control to create a nibble i/ o port. the output drivers are push/pull or open-drain, controlled by bit 2 of the pcon register. if one or both nibbles are required for i/o oper ation, they must be configured by writing to the port 0 mode register (p01m). after a hard ware reset or a stop mode recovery, port 0 is configured as an input port. port 0, bit 7 is used as the transmit output of the uart when uart tx is enabled.the i/o function of port 0, bit 7 is overridden by the uart serial output (txd) when uart tx is enabled (uctl[7] = 1). the pin must be configur ed as an output for txd data to reach the pin (p0m[6] = 0). an optional pull-up transistor is available as an otp option on all port 0 bits with nibble select. for information on configuration, see figure 4 on page 13. table 7. i/o port control registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no 000 0?3 00 port 0 p0 xxh 21 002 0?3 02 port 2 p2 xxh 23 003 0?3 03 port 3 p3 0xh 25 0f6 all f6 port 2 mode register p2m ffh 22 0f7 all f7 port 3 mode register p3m x x x x _ x 0 0 0b 24 0f8 all f8 port 0 mode register p01m x1 xx_xxx1b 20 f00 f 00 port configuration register pcon x x x x _ x 1 x 0b 20
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 13 port 2 port 2 is an 8-bit, bidirectional, cmos-com patible i/o port. its eight i/o lines can be independently configured under software cont rol as inputs or outputs. port 2 is always available for i/o operation. an eprom option bit is available to connect eight pull-up transistors on this port. bits programmed as outputs are globally programmed as either push/pull or open-drain. the power-on reset fu nction resets with the eight bits of port 2 [p27:20] configured as inputs. port 2 also has an 8-bit input or and and gate and edge detection circuitry, which can be used to wake up the part. p20 can be progr ammed to access the edge-detection circuitry in demodulation mode. for information on configuration, see figure 5 on page 14. figure 4. port 0 configuration zlp12840 otp mcu 4 4 port 0 (i/o) i/o open-drain out in pad resistive pull-up transistor (otp option) v cc
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 14 port 3 port 3 is a 8-bit, cmos-compatible fixed i/o port. port 3 consists of four fixed inputs (p33:p30) and four fixed outputs (p37:p34). p30, p31, p32, and p33 are standard cmos inputs, and can be configured under software co ntrol as interrupts, as receive data input to the uart block, as input to co mparator circuits, or as input to the ir learning amp. p34, p35, p36, and p37 are push/pull outputs, and can be configured as outputs from the counter/timers. for informa tion on configuration, see figure 6 on page 15. figure 5. port 2 configuration zlp12840 otp mcu port 2 (i/o) i/o open-drain out in pad resistive pull-up transistor (otp option) v cc
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 15 p31 can be used as an interru pt, analog comparator input, infrared learning amplifier input, normal digital input pin and as a stop mode recovery source. when bit 2 of the port 3 mode register (p3m) is set, p31 is used as the infrared learning amplifier, ir1. the reference source for ir1 is gnd. the infrared learning amplifier is disabled during stop mode. when bit 1 of p3m is set, the part is in analog mode and the analog comparator, comp1 is used. the reference voltage for comp1 is p30 (p ref1 ). when in analog mode, p30 cannot be read as a digital inpu t when the cpu reads bit 0 of the port 3 figure 6. port 3 configuration port 3 (i/o) zlp12840 otp mcu p30 p31 p32 p33 p34 p35 p36 p37 p3m register, 0f7h from stop-mode recovery source of smr 1 = analog; ir amp on 0 = digital; ir amp off irq2, p31 data latch irq0, p32 data latch irq1, p33 data latch digital d1 p31 (an1) p31 i ref p30 (p ref1 ) comp1 ir1 learning amplifier comp2 + + + d1 d2
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 16 register; such reads always return a valu e of 1. also, when in analog mode, p31 cannot be used as a stop mode recovery sour ce because in stop mode, the comparator is disabled, and its output will not toggle. the programming of bit 2 of the p3m register takes precedence over the programming of b it 1 in determining the function of p31. if both bits are set, p31 functions as an ir learning amplifier instead of an analog comparator. the output of the function selecte d for p31 can be used as a source for irq2 interrupt assertion (see figure 6 on page 15). the irq2 interrupt can be configured to be based upon detecting a rising, falling, or edge -triggered input change using bit 6 and bit 7 of the irq register. the p31 output stage si gnal also goes to the counter/timer edge detection circuitry similar to p20. p32 can be used as an interru pt, analog comparator, uart re ceiver, normal digital input and as a stop mode recovery source. when bit 6 of uctl is set, p32 functions as a receive input for the uart. when bit 1 of the p3 m register is set, thereby placing the part into analog mode, p32 functions as an anal og comparator, comp2. the reference voltage for comp2 is p33 (p ref 2). p32 can be used as a risi ng, falling or edge-triggered interrupt, irq0, using irq register bits 6 and 7. if uart receiver interrupts are not enabled, the uart receive interrupt is used as the source of interrupts for irq0 instead of p32. when in analog mode p32 cannot be used as a stop mode recovery source because the comparators are tu rned off in stop mode. when in analog mode, p33 cannot be read through bit 3 of the port 3 register as a digital input by the cpu. in this case, a read of bit 3 of the port 3 register indicates whether a stop mode recovery condition exists. reading a value of 0 indicates that a stop mode recovery condition does exist; if th e zlp12840 mcu is presently in stop mode, it will exit stop mode. reading a value of 1 in dicates that no condition exists to remove the zlp12840 from stop mode. additionally , when in analog mode, p33 cannot be used as an interrupt source. instead, the exis tence of a stop mode recovery condition can generate an interrupt, if enab led. p33 can be used as a falling-edge interrupt, irq1, when not in analog mode. irq1 is also used as the uart t x interrupt and the uart brg interrupt. only one source is active at a time. if bits 7 and 5 of uctl are set to 1, irq1 will transmit an interrupt when the transmit shift register is empty. if bits 0 and 5 of uctl are set to 1 and bit 6 of uctl is clear ed to 0, the brg interrupts will activate irq1. comparators and the ir am plifier are powered down by entering stop mode. for p30:p33 to be used as a stop mode reco very source during stop mode, these inputs must be placed into digital mode. when in analog mode, do not configure any port 3 input as a stop mode recovery source. the conf iguration of these inputs must be re-ini- tialized after stop mode re covery or power-on reset. note:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 17 2 port 3 also provides output for each of the counter/timers and the and/or logic (see figure 7 ). control is performed by programming ctr1 bits 5 and 4, ctr0 bit 0, and ctr2 bit 0. table 8. summary of port 3 pin functions pin i/o counter/timers comparator interrupt iramp uart p30 in ref1 p31 in in an1 irq2 ir1 p32 in an2 irq0 uart rx p33 in ref2 irq1 p34 out t8 ao1 irout p35 out t16 p36 out t8/t16 p37 out ao2
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 18 figure 7. port 3 counter/timer output configuration v pcon, bit 0 pad p35 data t16_out p34 data t8_out ctr2, bit 0 ctr0, bit 0 p36 data t8/16_out p37 data comp2 ctr1, bit 6 mux mux mux mux p34 pad p35 pad p36 dd v dd v dd pcon, bit 0 mux pad p37 v dd p32 p33 p32 p3m d1 + p31 comp1 i ref p30 p3m d1 p3m d2 + ir1 +
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 19 comparator inputs in analog mode, p31 and p32 have a comparator front end. the comparator reference is supplied by p33 and p ref1 . in this mode, the p33 internal data latch and its correspond- ing irq1 are diverted to the stop mode recovery sources (excluding p31, p32, and p33) as displayed in figure 6 on page 15. in digital mode, p33 is used as bit 3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p30:p33 to be used as a stop mode recovery source, these inputs must be placed into digital mode. comparator outputs the comparators can be programmed to be ou tput on p34 and p37 by setting bit 0 of the pcon register. port configuratio n register (pcon) the port configuration (pcon) register ( table 9 ), configures the port 0 output mode and the comparator output on port 3. the pcon register is located in expanded register bank f, address 00h. table 9. port configuration register (pcon) bit 7 6 5 4 3 2 1 0 field reserved port 0 output mode reserved comp./ir amp. output port 3 reset x x x x x 1 x 0 r/w ?w?w address bank f: 00h; linear: f00h bit position value description [7:3] ? reserved?writes have no effect; reads 11111b. [2] 0 1 port 0 output mode?controls the output mode of port 0. write only; reads return 1. open-drain push/pull [1] ? reserved?writes have no effect; reads 1. [0] 0 1 comparator or ir amplifier output port 3? select digital outputs or comparator and ir amplifier outputs on p34 and p37. write only; reads return 1. p34 and p37 outputs are digital. p34 is comparator 1 or ir amplifier output, p37 is comparator 2 output. note:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 20 this register is not reset after a smr. port 0 mode register the port 0 mode register determines the i/o direction of port 0. the port 0 direction is nibble-programmable. bit 6 controls the upper ni bble of port 0, bits [7:3]. bit 0 controls the lower nibble of port 0, bits [3:0] ( table 10 ). only p00, p01, and p07 are available on zlp12840 mcu 20-pin configurations. table 10. port 0 mode register (p01m) bit 7 6 5 4 3 2 1 0 field reserved p07:p04 mode reserved p03:p00 mode reset x 1 xxxxx 1 r/w ? w ????? w address bank independent: f8h; linear: 0f8h bit position value description 7 0 reserved?writes have no effect. reads 1b. [6] 0 1 p07:p04 mode output. input. [5:1] ? reserved?writes have no effect. reads 11111b. [0] 0 1 p00:p03 mode output. input. note: note:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 21 port 0 register the port 0 register allows read and write access to the port 0 pins ( table 11 ). only p00, p01, and p07 are available on zlp12840 mcu 20-pin configurations. table 11. port 0 register (p0) bit 7 6 5 4 3 2 1 0 field p07 p06 p05 p04 p03 p02 p01 p00 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank 0?3: 00h; linear: 000h bit position r/w description [7] read 0 1 write 0 1 port 0 pin 7?available for i/o if uart tx is disabled. (pin configured as input or output in p01m register). pin level is low. pin level is high. (pin configured as output in p01m register, uctl[7]=0). assert pin low. assert pin high if configured as push-pull; make pin high-impedance if it is open-drain. [6:0] read 1 write 0 1 port 0 pins 6?0?each bit provides ac cess to the corresponding port 0 pin. (pin configured as input or output in p01m register). pin level is low. pin level is high. (pin configured as output in p01m register). assert pin low. assert pin high if configured as push-pull; make pin high-impedance if it is open-drain. note:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 22 port 2 mode register the port 2 mode register determines the i/o di rection of each bit on port 2. bit 0 of the port 3 mode register determines whether th e output drive is push/pull or open-drain ( table 12 ). this register is not reset after a smr. table 12. port 2 mode register (p2m) bit 7 6 5 4 3 2 1 0 field p27 i/o definition p26 i/o definition p25 i/o definition p24 i/o definition p23 i/o definition p22 i/o definition p21 i/o definition p20 i/o definition reset 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f6h; linear: 0f6h bit position value description [7] 0 1 defines p27 as output. defines p27 as input. [6] 0 1 defines p26 as output. defines p26 as input. [5] 0 1 defines p25 as output. defines p25 as input. [4] 0 1 defines p24 as output. defines p24 as input. [3] 0 1 defines p23 as output. defines p23 as input. [2] 0 1 defines p22 as output. defines p22 as input. [1] 0 1 defines p21 as output. defines p21 as input. [0] 0 1 defines p20 as output. defines p20 as input. note:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 23 port 2 register the port 2 register allows read and write access to the port 2 pins ( table 13 ). table 13. port 2 register (p2) bit 7 6 5 4 3 2 1 0 field p27p26p25p24p23p22p21p20 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank 0?3: 02h; linear: 002h bit position value description [7:0] read 0 1 write 0 1 port 2 pins 7?0?each bit provides ac cess to the corresponding port 2 pin. (pin configured as input or output in p2m register). pin level is low. pin level is high. (pin configured as output in p2m register). assert pin low. assert pin high if configured as push-pull; make pin high-impedance if it is open-drain.
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 24 port 3 mode register the port 3 mode register is used primarily to configure the functionality of the port 3 inputs. when bit 2 is set, the ir learning amplifier is used instead of the comp1 comparator, regardless of the value of bit 1 ( table 14 ). this register is not reset after a smr. table 14. port 3 mode register (p3m) bit 7 6 5 4 3 2 1 0 field reserved ir learning amplifier digital/analog mode port 2 open- drain reset x x x x x 0 0 0 r/w ????? w w w address bank independent: f7h; linear 0f7h bit position r/w value description [7:3] ? ? reserved?writes have no effect. reads return 11111b. [2] w0 1 ir learning amplifier disabled. ir learning amplifier enabled with p31 configured as amplifier input. [1] w 0 1 digital/analog mode p30, p31, p32, p33 are digital inputs. p30, p32, and p33 are comparator inputs. if p3m[2]=0, p31 is also a comparator input. if p3m[2]=1, p31 is the ir amplifier input. [0] w0 1 port 2 open-drain. port 2 push/pull. note:
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 25 port 3 register the port 3 register allows read access to po rt pins p33 through p30 and write access to the port pins p37 through p34 ( table 15 ). table 15. port 3 register (p3) bit 7 6 5 4 3 2 1 0 field p37 p36 p35 p34 p33 p32 p31 p30 reset 0 0 0 0 x x x x r/w r/w r/w r/w r/w r/w r/w r/w r/w address banks 0?3: 03h; linear: 003h bit position value description [7] write 0 1 port 3, pin 7 output?writes to this bit do not affect the pin state if write-only register bit pcon[0] has been written with a 1, which configures p37 as the comparator 1 or ir amplifier output. p37 asserted low if pcon[0]=0. p37 asserted high if pcon[0]=0. a read returns the last value written to this bit. [6] write 0 1 port 3, pin 6 output?writes to this bit do not affect the pin stat e if register bits ctr1[7:6]=01, which configures p36 as the timer 8 and timer 16 combined logic output. p36 asserted low. p36 asserted high. a read returns the last value written to this bit. [5] write 0 1 port 3, pin 5 output?writes to this bit do not affect the pin st ate if register bit ctr2[0]=1, which configures p35 as the timer 16 output. p35 asserted low. p35 asserted high. a read returns the last value written to this bit. [4] write 0 1 port 3, pin 4 output?writes to this bit do not affect the pin state if write only register bit pcon[0]=1, which configures p34 as comparat or 2 output, or register bit ctr0[0]=1, which configures p34 as timer 8 output. p34 asserted low. p34 asserted high. a read returns the last value written to this bit.
ps024410-0108 p r e l i m i n a r y i/o port pin functions zlp12840 otp mcu product specification 26 this register is not reset after a smr. [3] read 0 1 0 1 port 3, pin 3 input?writin g this bit has no effect. if p3m[1]=0: p33 is low. p33 is high. if p3m[1]=1 or smr4[4]=1: smr condition exists. smr condition does not exist. [2] read 0 1 0 1 port 3, pin 2 input?writin g this bit has no effect. if p3m[1]=0: p32 input is low. p32 input is high. if p3m[1]=1: comparator 2 output is low. comparator 2 output is high. [1] read 0 1 0 1 0 1 port 3, pin 1 input?writin g this bit has no effect. if p3m[2:1]=00: p31 input is low. p31 input is high. if p3m[2:1]=01: comparator 1 output is low. comparator 1 output is high. if p3m[2:1]=10 or 11: ir amplifier output is low. ir amplifier output is high. [0] read 0 1 1 port 3, pin 0 input?writin g this bit has no effect. if p3m[1]=00: p30 input is low. p30 input is high. if p3m[1]=1: reads as 1. bit position value description note:
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 27 memory and registers the z8 lxm cpu used in the zlp12840 family of devices incorporates special features to extend the available me mory space while maintaining the benefits of a z8 ? cpu core in consumer and battery-operated applications. otp program/constant memory the zlp12840 family of devices can address up to 128 kb of one-time programmable (otp) memory, used for object code (program instructions and immediate data) and constant data (rom tables and data constants). the amount of otp implemented depends on the specific device. the otp memory sp ace is organized in 64 kb pages with the following characteristics. page 0 can contain up to 64 kb of program instructions and constant data. the first 12 bytes of page 0 are reserved for the six ava ilable 16-bit interrupt request (irq) vectors. upon reset, program execution begins at addre ss 000ch in page 0. execution rolls over to the bottom of page 0 if the program counte r exceeds the highest page 0 address (ffffh). page 1, if implemented, can contain up to 64 kb of data constants and tables only. page 1 cannot contain program instructions or immediate data. constant data in either page can be accessed only by the load constant (ldc and ldci) instructions. ldc and ldci use 16-bit addresses to access otp memory. for example, if a zlp12840 fami ly device contains 96 kb of otp memory, only the first 64 kb (page 0) can contain ob ject code; the remaining 32 kb (in page 1) is available for constant data. for a zlp12840 fa mily device with 64 kb or less of total otp memory, all otp memory is available for object code or constant data. the page accessed by ldc or ldci depend s on the value of program memory page register bit 0 (pmpr[0]). page 0 is accessed if pmpr[0]=0; page 1 is accessed if pmpr[0]=1. pmpr[7] enables the page toggle feature. for example, if pmpr[0]=0, pmpr[7]=1, and a load constant and increm ent (ldci) instruction address increments past ffffh, the state of pmpr[0] is toggled from 0 to 1, and the next ldci instruction addresses 0000h on page 1. figure 8 on page 28 displays the program/constant memory map for a 128 kb device.
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 28 register file this device features 1056 bytes of register f ile space, organized in 256 byte banks. bank 0 contains 237 bytes of ram addressed as gene ral-purpose registers, 4 port addresses (of which one is reserved), and 16 control register addresses. banks 1, 2, and 3 each contain 256 general-purpose register bytes. banks d and f each contain 16 addresses for control registers. all other banks are reserved and must not be selected. the current bank is selected for 8-bit direct or indirect addressing by writing register pointer bits rp[3:0]. in the current bank, a 16-byte working register group (addressed as r0?r15) is selected by writing rp[7:4]. a wo rking register operand requires only 4 bits of program memory. there are 16 working register groups per bank. see figure 9 on page 30 and figure 10 on page 31. figure 8. program/constant memory map (128 kb device) program irq 0?5 or 000ch (reset) page 0 vectors constants only page 1 0000h = 16-bit address (in page) {0, 0000h} = {pmpr[0], 16-bit address } (ldc, ldci only) not to scale constants {1, 0000h} {1, ffffh} {0, 0000h} {0, ffffh} ffffh 0000h ffffh
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 29 8-bit addresses in the range f0h?ffh (and the equivalent 4-bit addresses) are bank- independent, meaning they always access the cont rol registers in bank 0, regardless of the rp[3:0] value. addresses in the range 00h?03h always access the bank 0 port registers unless bank d or f is selected. (port 01h is not implemented in this device.) when bank d or f is selected, addresses 10h?efh access the bank 0 general-purpose registers. the ldx and ldxi instructions or indire ct addressing can be used to access the bank 1?3 registers not accessible by 8-bit or working register addresses (12-bit addresses 100h?103h, 1f0h?1ffh, 200h?203h, 2f0h?2ffh, 300h?303h, and 3f0h?3ffh). see linear memory addressing on page 32. stack the stack pointer register (spl) is bank 0 register ffh. operations that use the stack pointer always addresses bank 0, regardless of the rp[3:0] setting. fo r details on stack, refer to z8 lxm cpu core user manual (um0183) . this device does not use a stack pointer high byte. bank 0 register feh can be used to store user data, see user data register on page 36.
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 30 figure 9. register file 8-bit banked address map f0h?ffh cpu control f0h?ffh cpu control ports 00h?03h general registers cpu control f0h?ffh 04h?efh purpose cpu control f0h?ffh cpu control f0h?ffh bank 0 banks 1?3 bank 0 peripheral 00h?0fh bank d control bank 0 peripheral 00h?0fh bank f control = bank-independent address (always accesses bank 0) general registers 04h?efh purpose cpu control f0h?ffh ports 00h?03h general purpose registers 10h?efh general purpose registers 10h?efh * compiler?s default interrupt service routine working registers. not to scale
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 31 register pointer example r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 figure 10. register pointer?detail the upper nibble of the register file address provided by the register pointer specifies the active working register group. r7 r6 r5 r4 r3 r2 r1 r0 register pointer (rp), 0fdh the lower nibble of the register file address provided by the instruction points to the specified register r15 to r0 r15 to r4* ff f0 df d0 4f 40 3f 30 2f 1f 20 10 0f 00 * rp = 00: selects register bank 0, working register group 0 ef e0 specified working register group register group 0 register group 1 register group 2 i/o ports (banks 0? only) register group f r3 to r0* active group active bank
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 32 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = ctr3 the counter/timers are mapped into erf grou p d. access is easily performed using the following code segment. ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld r0,#xx ; load ctr0 ld 1, #xx ; load ctr1 ld r1, 2 ; ctr2 ctr1 ld rp, #7dh ; select expanded register bank d and working ; register group 7 of bank 0 for access. ld 71h, 2 ; ctr2 register 71h ld r1, 2 ; ctr2 register 71h linear memory addressing in addition to using the rp register to designate a bank and working register group for 8- bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in any other bark to or from a register in the current bank. linear addressing is implemented in the ldx and ldxi instructions only. linear addressing treats the register file as if all of the registers are logically ordered end-to-end, as opposed to being grouped into banks and working register groups, as displayed in figure 11 on page 33. for linear addressing, register file addresses are numbered sequentia lly from bank 0, register 00h to bank 0, register ffh, then continuing with bank 1, register 00h, and so on up to bank f, register ffh. using the ldx and/or the ldxi instructions, either the targ et or destination register location can be addressed through a 12-bit linea r address value stored in a general-purpose register pair. for example, the following code uses linear addressing for the source of a register transfer operation and uses a working register address for the target. srp #%23 ;set working register group 2 in bank 3 ld r0, #%55 ;load 55 into working register r0 in the current ;group and bank (linear address 320h) srp #%12 ;set working register group 1 in bank 2 ld r6, #%03 ;load high byte of source linear address (0320h) ld r7, #%20 ;load low byte of source linear address (0320h) ld r0, @rr6 ;load linear address 320h contents (55h) into ;working register r0 in the current group and ;bank (linear address 210h)
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 33 as it can be seen in the above example, the source register is referenced via a linear address value contained within registers r6 an d r7, whereas the destination is referenced via the srp setting and a working register. fo r more information on the use of the ldx and ldxi instruct ions, refer to z8 lxm cpu core user manual (um0183) . the lde and ldei in structions that existed in the z8 ? cpu are no longer valid; they are replaced by the ldx and ldxi instructions. program memory paging register bit 0 of the program memory paging register determines which 64 kb bank of program memory is read during the execution of the ldc and ldci instructions ( table 16 ). figure 11. register file ldx, ldxi linear 12-bit address map note: ports 000h?003h general registers typical stack cpu control purpose bank 0 banks 1?3 reserved peripheral d00h?d0fh bank d control reserved peripheral f00h?f0fh bank f control not to scale general purpose registers 004h?0efh 100h?3ffh d10h?dffh below 0d0h 0f0h?0ffh f10h?fffh
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 34 table 16. program memory paging register (pmpr) bit 7 6 5 4 3 2 1 0 field page toggle enable reserved page register reset 0 xxxxxx 0 r/w r/w ?????? r/w address bank independent: f0h; linear: 0f0h bit position value description [7] 0 1 page toggle enable pmpr[0] changes only wh en written by software. if pmpr[0]=0, the cpu toggles pmpr[0] when ldci increm ents past ffffh. [6:1] ? reserved?reads 111111b; write 000000b for compat ibility with possible future devices. [0] 0 1 page register ldc, ldci instructions access page 0. ldc, ldci instructions access page 1.
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 35 register pointer register the upper nibble of the register pointer ( table 17 ) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. th e lower nibble selects the expanded register file ba nk and, in the case of the zlp12840 mcu family, banks 0, 1, 2, 3, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed. any other value from 01h to 0fh exchanges the lower 16 registers to an expanded register bank. table 17. register pointer register (rp) bit 7 6 5 4 3 2 1 0 field working register group pointer register bank pointer reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fdh; linear 0fdh bit position value description [7:4] 0h?fh working register group pointer determines which 16 byte working group is addressed. [3:0] 0h?fh register bank pointer determines which bank is active.
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 36 user data register bank-independent register feh is available for user data storage ( table 18 ). do not use register feh as a co unter for the djnz instruction. stack pointer register the stack pointer register contains the 8-b it address of the stack pointer. the stack pointer resides in bank 0 of ram. the st ack address is decremented prior to a push operation and incremented after a pop operatio n. the stack address always points to the data stored at the ?top? of the stack (the lowe st stack address). during a call instruction, the contents of the program counter are saved on the stack. interrupts cause the contents of the program counter and flags registers to be saved on the stack. an overflow or underflow can occur when the stack address is incremented or decremented during normal operations. you must prevent this occurren ce otherwise, it results in unpredictable operations ( table 19 ). table 18. user data register (user) bit 7 6 5 4 3 2 1 0 field user data reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: feh; linear: 0feh bit position value description [7:0] 00h?ffh user data note:
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 37 table 19. stack pointer register (spl) bit 7 6 5 4 3 2 1 0 field stack pointer reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: ffh; linear: 0ffh bit position description [7:0] stack pointer
ps024410-0108 p r e l i m i n a r y memory and registers zlp12840 otp mcu product specification 38
ps024410-0108 p r e l i m i n a r y register file summary zlp12840 otp mcu product specification 39 register file summary table 20 maps each linear (12-bit) register file address to the associated register, mne- monic, and reset value. the table also lists th e register bank (or ba nks) and corresponding 8-bit address, if any, for each register, plus a page link to the de tailed register diagram. throughout this document, an ?x? in a numbe r denotes an undefined digit. a ??? (dash) in a table cell indicates that the corresponding attribute does not apply to the listed item. reset value digits highlighted in grey are not reset by a stop mode recovery. register bit smr[7] (shown in boldface ) is set to 1 instead of reset by a stop mode recovery. table 20. register file address summary address (hex) reset 12-bit bank 8-bit register description mnemonic page no 000 0?3 00 port 0 p0 xxh 21 001 0?3 01 reserved ? ? ? 002 0?3 02 port 2 p2 xxh 23 003 0?3 03 port 3 p3 0xh 25 004?00f 0 04?0f general-purpose registers (bank 0 only) ? xxh ? 010?0ef 0,d,f 10?ef general-purpose registers (banks 0, d, f) ? xxh ? 0f0 all f0 program memory paging register pmpr 0 xxx_xxx0 b 34 0f1 all f1 uart receive/transmit data register urdata/ utdata xxh 54 0f2 all f2 uart status register ust 0000_0010b 55 0f3 all f3 uart control register uctl 00h 56 0f4 all f4 uart baud rate generator constant bcnst ffh 57 0f5 all f5 reserved ? ? ? 0f6 all f6 port 2 mode register p2m ffh 22 0f7 all f7 port 3 mode register p3m x x x x _ x 0 0 0b 24 0f8 all f8 port 0 mode register p01m x1 xx_xxx1 b 20 0f9 all f9 interrupt pr iority register ipr xxh 90 0fa all fa interrupt request register irq 00h 92
ps024410-0108 p r e l i m i n a r y register file summary zlp12840 otp mcu product specification 40 0fb all fb interrupt mask register imr 0 xxx_xxxxb 89 0fc all fc flags register flags xxh 118 0fd all fd register pointer rp 00h 35 0fe all fe user data register user xxh 36 0ff all ff stack pointer register spl xxh 37 100?103 ? ? general-purpose registers (12-bit only) ? xxh ? 104?1ef 1 04?ef general-purpose registers ? xxh ? 1f0?203 ? ? general-purpose registers (12-bit only) ? xxh ? 204?2ef 2 04?ef general-purpose registers ? xxh ? 2f0?303 ? ? general-purpose registers (12-bit only) ? xxh ? 304?3ef 3 04?ef general-purpose registers ? xxh ? 3f0?3ff ? ? general-purpose registers (12-bit only) ? xxh ? 400?cff ? ? reserved ? ? ? d00 d 00 counter/timer 8 control register ctr0 000 0_ 0 0 00b 77 d01 d 01 timer 8 and timer 16 common functions ctr1 00 0 0_0000b 79 d02 d 02 counter/timer 16 control register ctr2 000 0_ 0 000b 82 d03 d 03 timer 8/timer 16 control register ctr3 00 0 0_ 0 xxxb 83 d04 d 04 counter/timer 8 low hold register tc8l 00h 76 d05 d 05 counter/timer 8 high hold register tc8h 00h 76 d06 d 06 counter/timer 16 low hold register tc16l 00h 75 d07 d 07 counter/timer 16 hi gh hold register tc16h 00h 75 d08 d 08 timer 16 capture low register lo16 00h 74 d09 d 09 timer 16 capture high register hi16 00h 74 d0a d 0a timer 8 capture low register lo8 00h 73 d0b d 0b timer 8 capture high register hi8 00h 73 d0c d 0c low-voltage detection register lvd 1111_1000b 98 d0d?d0f d 0d?0f reserved ? ? ? d10?dff ? ? reserved (8-bit access goes to bank 0) ? ? ? table 20. register file address summary (continued) address (hex) reset 12-bit bank 8-bit register description mnemonic page no
ps024410-0108 p r e l i m i n a r y register file summary zlp12840 otp mcu product specification 41 f00 f 00 port configuration register pcon x x x x _ x 1 x 0b 19 f01?f09 f 01?09 reserved ? ? ? f0a f 0a stop mode recovery register 4 smr4 x x x 0 _ 0 0 0 0b 111 f0b f 0b stop mode recovery register smr 0 0 1 0_ 0 0 00 b 102 f0c f 0c stop mode recovery register 1 smr1 00h 105 f0d f 0d stop mode recovery register 2 smr2 x 0 x 0 _ 0 0 x xb 107 f0e f 0e stop mode recovery register 3 smr3 x0h 110 f0f f 0f watchdog timer mode register wdtmr x x x x _ 1 1 0 1b 112 f10?fff ? ? reserved (8-bit access goes to bank 0) ? ? ? table 20. register file address summary (continued) address (hex) reset 12-bit bank 8-bit register description mnemonic page no
ps024410-0108 p r e l i m i n a r y register file summary zlp12840 otp mcu product specification 42
ps024410-0108 p r e l i m i n a r y infrared learning amplifier zlp12840 otp mcu product specification 43 infrared learning amplifier the zlp12840 mcu?s infrared learning amplifier allows you to detect and decode infra- red transmissions directly from the output of the receiving diode without the need for external circuitry. see port 3 on page 14. an ir diode can be connected to the ir amplifier as displayed in figure 12 . when the ir amplifier is enabled and an input current is detected on port 3, pin 1 (p31), the ir amplifier outputs a logical high value. wh en the input current is below the switching threshold of the ir amplifier, the am plifier outputs a logical low value. within the mcu, the ir amplifier output go es to the capture/timer logic, which can be programmed to demodulate the ir signal. the ir amplifier output can also be read by the cpu, or drive the port 3, pin 4 (p34) output if write-only register bit pcon[0] is written with a 1. the ir learning amplifier can demodulate signal s up to a frequency of 500 khz. a special mode exists that allows you to capture the third, fourth, and fifth edges of the ir amplifier output and generate an interrupt. for details on programming the timers to demodulate a received signal, see timers on page 59. figure 12. learning amplification circuitry with the zlp12840 mcu v cc d1 photodiode p31 of mcu
ps024410-0108 p r e l i m i n a r y infrared learning amplifier zlp12840 otp mcu product specification 44
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 45 universal asynchronous receiver/transmitter the universal asynchronous re ceiver/transmitter (uart) is a full-duplex communication channel capable of handling asynchronous da ta transfers. the two uarts use a single 8-bit data mode with selectable pa rity. features of the uarts include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? one or two stop bits ? separate transmit and receive interrupts ? framing, overrun, and break detection ? separate transmit and receive enables ? 8-bit baud rate generator (brg) ? baud rate generator timer mode ? uart operational during halt mode architecture the uarts consist of three primary functional blocks: transmitter, receiver, and baud rate generator. the uart tr ansmitter and receiver function independently, but employ the same baud rate and data format. figure 13 on page 46 displays the uart architecture. table 21. uart control registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no 0f1 all f1 uart receive/transmit data register urdata/ utdata xxh 54 0f2 all f2 uart status register ust 0000_0010b 55 0f3 all f3 uart control register uctl 00h 56 0f4 all f4 uart baud rate generator constant bcnst ffh 57
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 46 operation the uart channel can be used to communi cate with a master microprocessor or as a slave microprocessor, both of which exhibit transmit and receive functionality. you can either operate the uart channel by polling the uart status register or via interrupts. the uart remains active during halt mode. if ne ither the transmitter nor the receiver is enabled, the uart baud rate generator can be used as an additional timer. the uart contains a noise filter for the receiver that can be enabled. data format the uart always transmits and receives data in an 8-bit data format, with the least- significant bit occurring first. an even or odd parity bit can be optionally added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 14 and figure 15 on page 47 display the asynchronous data format employed by the uarts without parity and with parity, respectively. figure 13. uart block diagram receive shifter parity generator status register transmitter control transmit shift register receive data register transmit data register baud rate generator control registers rxd system bus txd
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 47 transmitting data us ing the polled method follow the steps below to transmit data using the polled method of operation: 1. write to the baud rate generator constant (bcnst) register, address 0f4h , to set the appropriate baud rate. 2. write a 0 to bit 6 of the p01m register. 3. write to the uart control register (uctl) to: (a) set the transmit enable bit, uctl[7], to enable the uart for data transmission. (b) if parity is appropriate, set the parity enable bit, uctl[4] to 1 and select either even or odd parity (uctl[3]). 4. check the transmit status register bit, ust[2], to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 6 . if the transmit data register is full (indicated by a 0), continue to monitor the ust[2] bit until the transmit data register becomes available to receive new data. 5. write the data byte to the uart transmit data register, 0f1h . the transmitter automatically transfers the data to the internal transmit shif t register and transmits the data. figure 14. uart asynchronous data format without parity figure 15. uart asynchronous da ta format with parity 1 1 lsb msb 0 2 idle state of line stop bit(s) data field bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start 1 1 lsb msb 0 2 idle state of line stop bit(s) data field bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 7 start
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 48 6. to transmit additional bytes, return to step 4 . 7. before disabling the transmitter, read th e transmit completion status bit, ust[1]. if ust[1]=0, continue to monito r the bit until it changes to 1, which indicates that all data in the transmit data and internal shift registers has been transmitted. data written while the transmit enable bit is clear (uctl[7] =0) will not be transmitted. data written while the transm it data status bit is clear (ust[2]=0) overwrites the previous value written, so the previous writte n value will not be transmitted. disabling the uart transmitter while the transmit comple tion status bit is clear (ust[1]=0) can corrupt the byte being transmitted. transmitting data using the interrupt-driven method the uart transmitter inte rrupt indicates the availability of the transmit data register to accept new data for transmission. follow th e steps below to configure the uart for interrupt-driven data transmission: 1. write to the bcnst register to set the appropriate baud rate. 2. write a 0 to bit 6 of the p01m register. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the appropriate priority. 5. write to the uart control register to: (a) set the transmit enable bit (uctl bit 7) to enable the uart for data transmission. (b) enable parity, if appropriate, a nd select either even or odd parity. 6. execute an ei instruc tion to enable interrupts. 7. because the transmit buffer is empty, an interrupt is immediately executed. 8. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the internal transm it shift register and transmits the data. 9. execute the iret instruction to return from the interrupt-s ervice routine and wait for the transmit data register to again become empty. 10. before disabling the transmitter, read th e transmit completion status bit, ust[1]. if ust[1]=0, continue to monito r the bit until it changes to 1, which indicates that all data in the transmit data and internal shift registers has been transmitted. data written while the transmit enable bit is clear (uctl[7] =0) will not be transmitted. data written while the transm it data status bit is clear (ust[2]=0) overwrites the previous value written, so the previous writte n value will not be transmitted. disabling the uart transmitter while the transmit comple tion status bit is clear (ust[1]=0) can corrupt the byte being transmitted. caution: caution:
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 49 receiving data using the polled method follow the steps below to configur e the uart for polled data reception: 1. write to the bcnst register to set the appropriate baud rate. 2. write to the uart control register (uctl) to: (a) set the receive enable bit (uctl[6 ]) to enable the uar t for data reception (b) enable parity, if appropriate an d select either even or odd parity 3. check the receive status bit in the uart st atus register, bit ust[7], to determine if the receive data register contains a valid da ta byte (indicated by a 1). if ust[7] is set to 1 to indicate available data, continue to step 4 . if the receive data register is empty (indicated by a 0), continue to monitor the ust[7] bit awaiting reception of the valid data. 4. read data from the uart receive data register. 5. return to step 3 to receive additional data. receiving data using the interrupt-driven method the uart receiver interrupt indicates the availability of new data (as well as error conditions). follow the steps below to config ure the uart receiver for interrupt-driven operation: 1. write to the uart brg constant registers to set the appropriate baud rate. 2. execute a di instruction to disable interrupts. 3. write to the interrupt control registers to enable the uart receiver interrupt and set the appropriate priority. 4. clear the uart receiver interrupt in th e applicable interrupt request register. 5. write to the uart control register (uctl) to: (a) set the receive enable bit (uctl[6]) to enable the uart for data reception. (b) enable parity, if appropriate, and select either even or odd parity. 6. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service rou tine (isr) performs the following: 1. checks the uart status register to determin e the source of the interrupt, whether it is an error, break, or received data. 2. reads the data from the uart receive data register if the interrupt was caused by data available.
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 50 3. clears the uart receiver interrupt in th e applicable interrupt request register. 4. executes the iret instruction to return from the interrupt serv ice routine and await more data. uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disab led, the baud rate generator can also function as a basic timer with interrupt capability. when the uart is set to run at higher baud rates, the uart receiver?s service routine might not have enough time to read and manipu late all bits in the uart status register (especially bits generating error conditions) for a received byte before the next byte is received. devise your own hand-shaking protocol to prevent the transmitter from transmit- ting more data while curren t data is being serviced. transmitter interrupts the transmitter generates a single interrupt wh en the transmit status bit, ust[2], is set to 1. this indicates th at the transmitter is ready to ac cept new data for transmission. the transmit status interrupt occurs after the intern al transmit shift register has shifted the first bit of data out. at this poin t, the transmit data register can be written with the next character to send. this provides 7 bit periods of latency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the ust[ 2] bit to 0. the in terrupt is cleared by writing a 0 to the transmit data register. receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte has been received and is available in the uart receive data register?this interrupt can be disabled independent of the other receiver interrupt sources. the received data interrupt occu rs once the receive character has been received and placed in the receive data register. software mu st respond to this received data available cond ition before the next characte r is completely received to avoid an overrun error. th e interrupt is cleared by reading from the uart receive data register. ? a break is received?a break is detected when a 0 is sent to the receiver for the full byte plus the parity and stop bits. af ter a break is detected, it will interrupt immediately if there is no valid data in the receive data register. if data is present in the receive data register, an interrupt will occur after the uart receive data register is read. ? an overrun is detected?an overrun occurs wh en a byte of data is received while there is valid data in the uart receive data register that is not read. the interrupt note:
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 51 will be generated when the uart receive data register is read. the interrupt is cleared by reading the uart receive data register. when an overrun error occurs, the additional data byte will not overwrite the data currently stored in the uart receive data register. ? a data framing error is detected?a data frami ng error is detected when the first stop bit is 0 instead of 1. when configured for 2 stop bits, a data framing error is only detected when the first stop bit is 0. a fra ming error interrupt is generated when the framing error is detected. reading the uart receive data register clears the interrupt. it is important to ensure that the transmitt er uses the same stop bit configuration as the receiver. uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus (ust) register is updated to indicate the overrun condition (and break detect, if appli cable). the ust[7] bit is set to 1 to indi- cate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain valid data and should be ignored. the break detect bit, ust[3], indicates if the overrun w as caused by a break condition on the line. after reading the status byte indicating an ove rrun error, the receive da ta register must be read again to clear the error bits is the uar t status 0 register. updates to the receive data register occur only when th e next data word is received. uart data and error handling procedure figure 16 on page 52 displays the recommended procedure for use in uart receiver interrupt service routines. note:
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 52 baud rate generator interrupts if the baud rate generator interrupt enable is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this action allows th e baud rate genera- tor to function as an additional counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is the system clock. the uart baud rate constant register contains an 8-bit baud rate divisor value (bcnst[7:0]) that sets the data figure 16. uart receiver interrupt service routine flow receiver ready receiver interrupt read status errors? discard data read data that clears the rda bit and resets the error bits read data no yes
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 53 transmission rate (baud rate) of the uart. for programmed register values other than 00h , the uart data rate is calculat ed using the following equation: when the uart baud rate low register is programmed to 00h , the uart data rate is calculated using the following equation: when the uart baud rate gene rator is used as a general-pu rpose counter, the counters time out period can be computed as follows based upon the counters clock input being a divide by 16 of the system clock and the maximum count value being 255: in general, the system clock frequency is the xtal clock frequency divided by 2. when the uart is disabled, the baud rate generator can function as a basic 8-bit timer with interrupt on time-out. follow the steps below to configure the baud rate generator as a timer with interrupt on time-out: 1. disable the uart by clearing the receive and transmit enable b its, uctl[7:6] to 0. 2. load the appropriate 8-bit count value into the uart baud rate generator constant register. the count frequency is the system clock frequency in hz divided by 16. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the baud rate generator bit (uctl bit 0) in the uart control register to 1. when configured as an 8-bit timer, the count value, instead of th e reload value, is read, and the counter begins counting do wn from its initial programmed value. upon timing out (reaching a value of 1), if the time-out in terrupt is enabled, an interrupt will be produced. the counter will then reload its programmed start value and begin counting down again. table 22 lists a number of bcnst register settings at various baud rate s and system clock frequencies. table 22. bcnst register settings examples target uart data rate (baud) system clock = 4 mhz, crystal clock = 8 mhz system clock = 3 mhz, crystal clock = 6 mhz 2400 bcnst = 01101000 actual baud rate = 2403 bcnst = 01001110 actual baud rate = 2403 uart data rate bits/s () system clock frequency hz () 16 uart baud rate divisor value bcnst () ------------------------------------------------------------------------------------------------------------------------------- --------- = uart data rate bits/s () system clock frequency hz () 4096 -------------------------------------------------------------------------------- - = time-out period s () 16 uart baud rate divisor value bcnst () system clock frequency mhz () ------------------------------------------------------------------------------------------------------------------------------- ---------- - = note:
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 54 uart receive data register/u art transmit data register the uart receive/transmit data register is used to send and retrieve data from the uart channel. when the uart receives a byte of data, it can be read from this register. the uart receive interrupt is cleared when th is register is used. data written to this register is transmitted by the uart ( table 23 ). 4800 bcnst = 00110100 actual baud rate = 4807 bcnst = 00100111 actual baud rate = 4807 9600 bcnst = 00011010 actual baud rate = 9615 bcnst = 00010100 actual baud rate = 9375 19200 bcnst = 00001101 actual baud rate = 19230 bcnst = 00001010 actual baud rate = 18750 table 23. uart receive/transmit data register (urdata/utdata) bit 7 6 5 4 3 2 1 0 field uart receive/transmit reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f1h; linear: 0f1h bit position description [7:0] uart receive/transmit when read, returns received data. when written, tran smits written data. table 22. bcnst register settings examples (continued) target uart data rate (baud) system clock = 4 mhz, crystal clock = 8 mhz system clock = 3 mhz, crystal clock = 6 mhz
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 55 uart status register the uart status register shows the status of the uart. bits [6:3] are cleared by reading the uart receive/transmit register ( f1h ) ( table 24 ). table 24. uart status register (ust) bit 7 6 5 4 3 2 1 0 field receive status parity error overrun error framing error break transmit data transmit complete noise filter reset 00000010 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f2h; linear: 0f2h bit position value description [7] 0 1 receive status?set when data is re ceived; cleared when urdata is read. uart receive data register empty. uart receive data register full. [6] 0 1 parity?set when a parity error occurs; cleared when urdata is read. no parity error occurs. parity error occurs. [5] 0 1 overrun?set when an overrun error occurs; cleared when urdata is read. no overrun error occurs. overrun error occurs. [4] 0 1 framing?set when a framing error occurs; cleared when urdata is read. no framing error occurs. framing error occurs. [3] 0 1 break?set when a break is detect ed; cleared when urdata is read. no break occurs. break occurs. [2] 0 1 transmit data status?set when the uart is ready to transmit; cleared when trdata is written. do not write to the uart transmit data register. uart transmit data register ready to receive additional data. [1] 0 1 transmit completion status data is curren tly transmitting. transmission is complete.
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 56 uart control register as the name implies, the uart register cont rols the uart. in addition to setting bit 5 (see table 25 ), also set appropriate bit in th e interrupt mask register (see table 45 on page 92). this register is not reset after a stop mode recovery. [0] read 0 1 noise filter?detects nois e during data reception. no noise detected. noise detected. write 0 1 turn off noise filter. turn on noise filter. table 25. uart control register (uctl) bit 7 6 5 4 3 2 1 0 field transmitter enable receiver enable uart interrupts enable parity enable parity select send break stop bits baud rate generator reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f3h; linear: 0f3h bit position value description [7] 0 1 transmitter disabled. transmitter enabled. [6] 0 1 receiver disabled. receiver enabled. [5] 0 1 uart interrupts disabled. uart interrupts enabled. [4] 0 1 parity disabled. parity enabled. bit position value description note:
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 57 baud rate generator constant register the uart baud rate generator determines the frequency at which uart data is received and transmitted. this baud rate is determined by the fo llowing equation: the system clock is usually the crystal clock divided by 2. when the uart baud rate generator is used as an additional timer, a read from this regis- ter will return the actual value of the count of the brg in progress and not the reload value ( table 26 ). this register is not reset after a stop mode recovery. [3] 0 1 even parity selected. odd parity selected. [2] 0 1 no break is sent. send break (force tx output to 0). [1] 0 1 one stop bit. two stop bits. [0] 0 1 baud rate generator?when the transmitter and receiver are disabled, the brg can be used as an additional timer. when setting this bit, clear bits [7:6] in this register. also set bit [5] if an interrupt is desired when the brg is reloaded. brg used as baud rate generator for uart. brg used as timer. table 26. baud rate generator constant register (bcnst) bit 7 6 5 4 3 2 1 0 field baud rate generator constant reset 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f4h; linear: 0f4h bit position value description uart data rate bits/s () system clock frequency hz () 16 uart baud rate divisor value bcnst () ------------------------------------------------------------------------------------------------------------------------------- ---------- - = note:
ps024410-0108 p r e l i m i n a r y universal asynchronous receiver/ zlp12840 otp mcu product specification 58 bit position description [7:0] brg constant when read, returns the actual ti mer count value (when uctl[0]=1). when written, sets the baud rate generato r constant. the actual baud rate frequency = xtal (32 x bcnst ).
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 59 timers the crimzon ? zlp12840 mcu infrared timer contai ns a 16-bit and an 8-bit counter/ timer, each of which can be used simultaneously for transmitting. in ad dition, both timers can be used for demodulating an input carrier wave. both tim ers share a single input pin. figure 17 displays the counter/timer architecture, which is designed to help unburden the program from coping with such real-time pr oblems as generating complex waveforms or receiving and demodulating co mplex waveforms and pulses. in addition to the 16-bit and 8-bit timers, th e uart?s baud rate generator can be used as an additional 8-bit timer when the uart receiver is not in use. see universal asynchro- nous receiver/transmitter on page 45. figure 17. counter/timers block diagram hi16 lo16 tc16h tc16l hi8 lo8 tc8h tc8l 8-bit timer 8 16-bit timer 16 timer 16 timer 8/16 sclk timer 8 and/or logic clock divider glitch filter edge detect circuit 8 8 8 8 8 16 8 8 8 1248
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 60 table 27 summarizes the registers used to control timers. some timer functions can also be affected by control registers for other peripheral functions. counter/timer functional blocks the crimzon zlp12840 mcu infrared timer co ntains a glitch filter for removing noise from the input when demodula ting an input carrier. each timer features its own demodulating mode. the t8 tim er has the ability to capt ure only one cycle of a carrier wave of a high-frequen cy waveform. each timer can be simultaneously used to generate a signal output. input circuit depending on the setting of register bits p3 m[2:1] and ctr1[6], the timer/counter input monitors one of the following conditions: ? the p31 digital signal, if ctr1[6]=0 and p3m[2:1]=00. ? the p31 analog comparator output, if ctr1[6]=0 and p3m[2:1]=01. ? the p31 ir amplifier output, if ctr1[6]=0 and p3m[2]=1. table 27. timer control registers address (hex) 12-bit bank 8-bit register description mnemonic reset page no d00 d 00 counter/timer 8 control register ctr0 000 0_ 0 0 00b 77 d01 d 01 timer 8 and timer 16 common functions ctr1 00 0 0_000 0 b 79 d02 d 02 counter/timer 16 control register ctr2 000 0_ 0 000b 82 d03 d 03 timer 8/timer 16 control register ctr3 00 0 0_ 0xxxb 83 d04 d 04 counter/timer 8 low hold register tc8l 00h 76 d05 d 05 counter/timer 8 high hold register tc8h 00h 76 d06 d 06 counter/timer 16 low hold register tc16l 00h 75 d07 d 07 counter/timer 16 high hold register tc16h 00h 75 d08 d 08 timer 16 capture low register lo16 00h 74 d09 d 09 timer 16 capture high register hi16 00h 74 d0a d 0a timer 8 capture low register lo8 00h 73 d0b d 0b timer 8 capture high register hi8 00h 73
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 61 ? the p20 digital signal, if ctr16=1. based on register bits ctr1[5:4], a pulse is generated at when a ri sing edge, falling edge, or any edge is detected. glitches in the input si gnal are filtered out if they are shorter than the glitch filter width specified in register bits ctr1[3:2]. the input ci rcuit is displayed in figure 18 . t8 transmit mode before t8 is enabled, the output of t8 depend s on ctr1, bit 1. if it is 0, t8_out is 1; if it is 1, t8_out is 0. see figure 19 . figure 18. counter/timer input circuit glitch filter 8 sclk reserved 4 sclk 00 10 11 01 edge detection ctr1[0] ctr1[1] 00 01 11 reserved 10 falling edge rising edge p31 comp. ir amp. p30 i ref p20 0 1 + + 0 1 ctr1[5:4] ctr1[3:2] ctr1[6] p3m[2] p3m[1] 0 1
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 62 figure 19. transmit mode flowchart load tc8l reset t8_out load tc8h set t8_out enable t8 no yes set time-out status bit (ctr0, bit 5) and generate timeout_int if enabled 1 0 t8 (8-bit) transmit mode t8_enable bit set ctr0, bit 7 no yes ctr1, bit 1 value 1 load tc8l reset t8_out load tc8h set t8_out enable t8 reset t8_enable bit set time-out status bit (ctr0 bit 5) and generate timeout_int if enabled no no t8_timeout yes yes single pass? modulo-n single pass 0 t8_out value t8_timeout
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 63 when t8 is enabled, the output t8_out switches to the initial value (ctr1, bit 1). if the initial value (ctr1, bit 1) is 0, tc8l is lo aded; otherwise, tc8h is loaded into the counter. in single-pass mode (ctr0, bit 6) , t8 counts down to 0 and stops, t8_out toggles, the time-out status bit (ctr0, bit 5) is set, and a time-out interrupt can be generated if it is enabled (ctr0, bit 1) . in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. from that point, t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8 _out, and sets the time-out status bit (ctr0, bit 5), thereby generating an interrupt if enab led (ctr0, bit 1). one cycle is thus completed. t8 then loads from tc8h or tc8l according to th e t8_out level and repeats the cycle (see figure 20 ). you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. an initial count of 1 is not allowed (a non-fu nction occurs). an init ial count of 0 causes tc8 to count from 0 to ffh to feh . the ?h? suffix denotes hexadecimal values. figure 20. 8-bit counter/timer circuits z8 lxm data bus z8 lxm dat a bus po si t i v e ed g e negative edge ctr0 data bit 2 irq4 ctr0 data bit 1 t8_out tc8l tc8h cl o ck se l e c t sclk ctr0 data bits [4:3] cl o ck hi8 lo8 8-bit co u n t er t8 (tc8) caution: note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 64 transition from 0 to ffh is not a time-out condition. using the same instructions for stopping the counter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counte r/timers must be stopped. sec- ond, the status bits must be reset. these commands are required because it takes one counter/timer clock interval for the initiated event to actually occur (see figure 21 and figure 22 ). t8 demodulation mode you must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1 bi ts [5:4]) is detected, it starts to count down. when a subsequent edge (rising, falling, or both depending on ctr1 b its [5:4]) is detected during counting, the current value of t8 is complemented and put in to one of the capture registers. if it is a positive edge, data is put in to lo8; if it is a negative edge, data is put figure 21. t8_out in single-pass mode figure 22. t8_out in modulo-n mode note: caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 data bit 1) t8_out toggles; time-out interrupt counter enable command, t8_out, switches to its initial value (ctr1 data bit 1) t8_out toggles t8_out tc8l tc8h tc8l tc8h tc8l time-out interrupt time-out interrupt
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 65 into hi8. from that point, one of the edge detect status bits (ctr1, bits [1:0]) is set, and an interrupt can be generated if enabled (ctr0, bit 2). me anwhile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the time-out status bit (ctr0, bit 5) is set, and an interrupt can be generated if enabled (ctr0, bit 1). t8 then continues counting from ffh (see figure 23 ). when bit 4 of ctr3 is enable d, the flow of the demodula tion sequence is altered. the third edge makes t8 active, and the fourth and fifth edges are captured. the capture figure 23. demodulation mode count capture flowchart t8 (8-bit) count capture t8_enable (set by user) no yes edge present? no yes what kind of edge? pos t8 lo8 neg t8 hi8 %ff t8
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 66 interrupt is activated after the fifth event o ccurs. this mode is us eful for capturing the carrier duty cycle as well as the frequency at which the first cycle is corrupted (see figure 24 and figure 25 on page 67). figure 24. demodulation mode flowchart t8 (8-bit) demodulation mode t8_enable ctr0, d7? no yes first edge present? no no t8_enable bit set? yes set edge present status bit and trigger data capture int. if enabled no %ff tc8 yes enable tc8 edge present? disable t8 yes t8 time out? yes set time-out status bit and trigger time out int. if enabled no continue counting
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 67 figure 25. demodulation mode flowchart with bit 4 of ctr3 set t8 (8-bit) demodulation mode t8_enable ctr0 bit 7 no yes third edge present no no t8_enable bit set yes no ffh tc8 yes enable tc8 disable t8 yes t8 time out yes set time-out status bit and trigger time out interrupt if enabled no continue counting fifth edge present yes set edge present status capture interrupt if enabled fourth edge present set edge present status bit and trigger data
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 68 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled, is dependent on ctr1, bit 0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enabled or not by programming ctr1 bits [3:2] to a 10 or 11. when bit 4 of ctr3 is set, the t16 output does not update. however, time-out interrupts (flags) are still updated. in addition, the t8 carrier is not disrupted by timing out of the t16 timer. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1, bit 0). when t16 counts down to 0, t16_out is toggled (in normal or ping-pong mode), an interrupt (c tr2, bit 1) is generated (if enabled), and a status bit (ctr2, bit 5) is set. see figure 26 . global interrupts override this function as described in the interrupts on page 85 . if t16 is in single-pass mode, it is stopped at this point (see figure 27 on page 69). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting continues (see figure 28 on page 69). figure 26. 16-bit counter/timer circuits po si t i v e ed g e negative edge ctr2 data bit 2 irq3 ctr2 data bit 1 t16_out tc16 tc16 cl o ck se l e c t sclk ctr2 data bits [4:3] cl o ck 16-bit co u n t er t16 (tc16) hi16 lo16 z8 lxm data bus z8 lxm data bus note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 69 you can modify the values in tc16h and tc16 l at any time. the new values take effect when they are loaded. do not load these registers at the time the values are to be loaded into th e counter/timer to ensure known operation. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to fffeh . transition from 0 to ffffh is not a time-out con- dition. t16 demodulation mode you must program tc16l and tc16h to ffh . after t16 is enabled, and the first edge (rising, falling, or both depend ing on ctr1 bits [5:4]) is de tected, t16 captures hi16 and lo16, reloads, and begins counting. if bit 6 of ctr2 is 0? when a subsequent edge (rising, falling, or both depending on ctr1 bits [5:4]) is detected during counting, the current count in t16 is complemented and put into hi16 and lo16. wh en data is captured, one of the edge detect status bits figure 27. t16_out in single-pass mode figure 28. t16_out in modulo-n mode caution: tc16h * 256 + tc16l counts counter enable command, t16_out, switches to its initial value (ctr1 data bit 0) t16_out toggles, time-out interrupt tc16h * 256 + tc16l counter enable command, t16_out, switches to its initial value (ctr1 data bit 0) t16_out toggles, time-out interrupt tc16h * 256 + tc16l tc16h * 256 + tc16l t16_out toggles, time-out interrupt t16_out
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 70 (ctr1, bit 1; bit 0) is set, and an interrupt is generated if enabled (ctr2, bit 2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). if bit 6 of ctr2 is 1? t16 ignores the subsequent edges in the input signal and continues counting down. a time-out of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, bit 2). in th is case, t16 does not reload and continues counting. if ctr2 bit 6 is toggled (by writing a 0 then a 1 to it), t16 captures and reloads on the next edge (rising, fallin g, or both depending on ctr1 bits [5:4]), continuing to ignore subsequent edges. this t16 mode generally measur es mark time, the length of an active carrier signal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 bit 5) is set, and an interrupt time-out can be generated if enabled (ctr2 bit 1). ping-pong mode this operation mode is only valid in trans mit mode. t8 and t16 must be programmed in single-pass mode (ctr0, bit 6; ctr2, bit 6), and ping-pong mode must be programmed in ctr1 bits [3:2]. you can begi n the operation by enabling either t8 or t16 (ctr0, d7 or ctr2, d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1, bit 1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is re ached, t8 is disabled, and t1 6 is enabled. t16_out then switches to its initial value (ctr1, bit 0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the termin al count, it stops, t8 is enabled again, repeating the entire cycle. interrupts can be allowed when t8 or t16 reaches terminal control (ctr0, bit 1; ctr2, bit 1). to stop the ping-pong operation, write 00 to bits ctr1 bits [3:2]. see figure 29 on page 71. enabling ping-pong operation while the counter/timers are ru nning might cause intermit- tent counter/timer function. di sable the counter/tim ers and reset the status flags before instituting this operation. note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 71 initiating ping-pong mode first, ensure that both coun ter/timers are not running. set t8 into single-pass mode (ctr0, bit 6), set t16 into single-pass mo de (ctr2, bit 6), and set the ping-pong mode (ctr1 bits [3:2]). these instructions are not con secutive and can oc cur in random order. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). the initial value of t8 or t16 must not be 1 . if you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alternately by hardware. the time-out bits (ctr0, bit 5; ctr2, bit 5) are set every time the counter/ timers reach the terminal count. timer output the output logic for the timers is displayed in figure 30 on page 72. p34 is used to output t8_out when bit 0 of ctr0 is set. p35 is us ed to output the value of t16_out when bit 0 of ctr2 is set. when bit 6 of ctr1 is set, p36 outputs the logic combination of t8_out and t16_out via bits [4:5] of ctr1. figure 29. ping-pong mode diagram enable tc8 time-out enable tc16 time-out ping-pong ctr1 data bits [3:2]
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 72 counter/timer registers timer 8 capture high register the timer 8 capture high register holds the captured data from the output of the 8-bit counter/timer 0. typically, this register contai ns the number of coun ts when the input sig- nal is 1 ( table 28 ). this register is not reset after a smr. figure 30. output circuit p35_internal t8_out ctr1 data bits [5:4] p34_internal ctr0 data bit 0 p36_internal ctr1 data bit 6 ctr2 data bit 0 p35 p36 p34 t16_out mux ctr1 data bit 2 ctr1 data bit 3 and/or/nor/nand logic mux mux mux note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 73 timer 8 capture low register the timer 8 capture low register holds the captured data from the output of the 8-bit counter/timer 0. typically, this register co ntains the number of counts when the input signal is 0 ( table 29 ). this register is not reset after a smr. timer 16 capture high register the timer 16 capture high register holds the captured data from the output of the 16-bit counter/timer 16. this register contains th e most-significant byte (msb) of the data ( table 30 ). this register is not reset after a smr. table 28. timer 8 capture high register (hi8) bit 7 6 5 4 3 2 1 0 field t8_capture_hi reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 0bh; linear: d0bh bit position value description [7:0] 0hh?ffh t8_capture_hi?reads return captured data. writes have no effect. table 29. timer 8 capture low register (l08) bit 7 6 5 4 3 2 1 0 field t8_capture_lo reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 0ah; linear: d0ah bit position value description [7:0] 0hh?ffh t8_capture_lo?read returns c aptured data. writes have no effect. note: note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 74 timer 16 capture low register the timer 16 capture low register holds the captured data from the output of the 16-bit counter/timer 16. this register contains the lsb of the data ( table 31 ). this register is not reset after a smr. counter/timer 16 high hold register the counter/timer 16 high hold register contains the high byte of the value loaded into the t16 timer ( table 32 ). this register is not reset after a smr. table 30. timer 16 capture high register (hi16) bit 7 6 5 4 3 2 1 0 field t16_capture_hi reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 09h; linear: d09h bit position value description [7:0] 0hh?ffh t16_capture_hi?read returns captured data. writes have no effect. table 31. timer 16 capture low register (l016) bit 7 6 5 4 3 2 1 0 field t16_capture_lo reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 08h; linear: d08h bit position value description [7:0] 0hh?ffh t16_capture_lo?read returns captured data. writes have no effect. note: note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 75 counter/timer 16 low hold register the counter/timer 16 low hold register contai ns the low byte of the value loaded into the t16 timer ( table 33 ). this register is not reset after a smr. counter/timer 8 hi gh hold register the counter/timer 8 high hold register cont ains the value to be counted while the t8 output is 1 ( table 34 ). this register is not reset after a smr. table 32. counter/timer 16 high hold register (tc16h) bit 7 6 5 4 3 2 1 0 field t16_data_hi reset 0 0 0 0 0 0 0 0 r/w r/wr/wr/wr/wr/wr/wr/wr/w address bank d: 07h; linear: d07h bit position value description [7:0] 0hh?ffh t16_data_hi?read/write data. table 33. counter/timer 16 low hold register (tc16l) bit 7 6 5 4 3 2 1 0 field t16_data_lo reset 0 0 0 0 0 0 0 0 r/w r/wr/wr/wr/wr/wr/wr/wr/w address bank d: 06h; linear: d06h bit position value description [7:0] 0hh?ffh t16_data_lo?read/write data. note: note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 76 counter/timer 8 low hold register the counter/timer 8 low hold register contai ns the value to be counted while the t8 output is 0 ( table 35 ). this register is not reset after a smr. counter/timer 8 control register the counter/timer 8 control register controls the timer function of the t8 timer. this bank d register is described in table 36 . writing a 1 to ctr0[5] is the only way to r eset the terminal count status condition. re- set this bit before usin g/enabling the counter/timers. table 34. counter/timer 8 high hold register (tc8h) bit 7 6 5 4 3 2 1 0 field t8_level_hi reset 0 0 0 0 0 0 0 0 r/w r/wr/wr/wr/wr/wr/wr/wr/w address bank d: 05h; linear: d05h bit position value description [7:0] 0hh?ffh t8_level_hi?read/write data. table 35. counter/timer 8 low hold register (tc8l) bit 7 6 5 4 3 2 1 0 field t8_level_lo reset 0 0 0 0 0 0 0 0 r/w bank d: 04h; linear: d04h address r/wr/wr/wr/wr/wr/wr/wr/w bit position value description [7:0] 0hh?ffh t8_level_lo?read/write data. note: caution:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 77 ensure to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode) when using the or or and commands. these instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value an d then written back into the registers. example : when the status of bit 5 is 1, a timer reset condition occurs. table 36. counter/timer 8 control register (ctr0) bit 7 6 5 4 3 2 1 0 field t8_enable single/ modulo-n time_out t8 _clock capture_int_m ask counter_int_m ask p34_out reset 000 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank d: 00h; linear: d00h bit position value description [7] 0 1 t8_enable?disable/enable the t8 counter. disable counter. enable counter. configure t8 properly before enabling it. [6] 0 1 single-pass/modulo-n modulo-n mode?counter reloads the initia l value when terminal count is reached. single-pass mode?counter stops when the terminal count is reached. [5] read 0 1 write 0 1 time_out?this bit is set when the t8 terminal count is reached. no counter time-out occurs. counter time-out occurred. no effect. reset flag to 0. software must reset this flag before us ing counter/timers. [4:3] 00 01 10 11 t8 _clock?select the t8 input clock frequency. these bits are not reset upon stop mode recovery. sclk. sclk 2. sclk 4. sclk 8. [2] 0 1 capture_int_mask?disable/enable interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. this bit is not reset upon stop mode recovery. disable data capture interrupt. enable data ca pture interrupt. note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 78 t8 and t16 common functions register the t8 and t16 common functions register (ctr1) controls the functions in common with timer 8 and timer 16. table 37 describes the bits for this register. take care to differentiate transmit mode from demodulation mode, as set by ctr1[7]. the functions of ctr1[6:0] and ctr2[6] are different depending on which mode is selected. do not change from one mode to another withou t first disabling the counter/timers. [1] 0 1 counter_int_mask?disable/enable t8 time-out interrupt. this bit is not reset upon stop mode recovery. disable time-o ut interrupt. enable time-out interrupt. [0] 0 1 p34_out?select normal i/o or t8 out put function for port 3, pin 4. p34 as port output. t8 output on p34. bit position value description note:
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 79 table 37. timer 8 and timer 16 common functions register (ctr1) bit 7 6 5 4 3 2 1 0 field mode p36 out/ demodulator input t8/t16 logic/ edge detect transmit submode/ glitch filter initial timer 8 out/ rising edge initial timer 16 out/ falling edge reset 00 0 00 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank d: 01h; linear: d01h bit position description [7] mode?selects the timer mode for signal transmission or demodulation. 0 1 transmit mode. demodulation mode. [6] transmit mode p36 out?select normal i/o or ti mer output on port 3, pin 6. 0 1 p36 acts as normal i/o port output. p36 acts as combined timer 8/timer 16 output. demodulation mode demodulator input?select port 2, pin 0 or port 3, pin 1 as the counter/timer input. 0 1 p31 acts as the demodulator input. if imr[2] = 1, a p31 event can also generate an irq1 interrupt. to prevent this, clear imr[2] or select p20 as input instead. p20 acts as the demodulator input. [5:4] transmit mode t8/t16 logic?defines how the timer 8/timer 16 outputs are combined logically. these bits are not reset upon stop mode recovery. 00 01 10 11 output is t8 and t16. output is t8 or t16. output is t8 nor t16. output is t8 nand t16. demodulation mode edge detect?define the behavior of the edge detector. 00 01 10 11 falling edge detection. rising edge detection. falling and rising edge detection. reserved.
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 80 [3:2] transmit mode submode selection?select normal or ping-p ong mode operation, or force t16 output. when these bits are written to 00b (n ormal mode) or 01b (ping-pong mode), t16_out assumes the opposite state of bit ctr1[0] until the timer begins counting. 00 01 10 11 normal operation. writing 00 terminate s ping-pong mode, if it is active. ping-pong mode. force t16_out = 0. force t16_out = 1. demodulation mode glitch filter?define the maxi mum glitch width to be reje cted by the counter/timer. 00 01 10 11 no filter. 4 sclk cycle filter. 8 sclk cycle filter. reserved. [1] transmit mode initial timer 8 out?select th e initial t8_out state when timer 8 is enabled. while the timer is disabled, the opposite state is asse rted on the pin to ensure that a transition occurs when the timer is enabled. changing this bit while the counter is enabled can cause unpredictable output on t8_out. 0 1 t8_out transitions from high to low when timer 8 is enabled. t8_out transitions from low to high when timer 8 is enabled. demodulation mode rising edge?indicates whether a rising edge was detected on the input signal. write 1 to this flag to reset it. read 0 1 write 0 1 no rising edge detection. rising edge detection. no effect. reset flag to 0. bit position description
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 81 [0] transmit mode initial timer 16 out?in no rmal or ping-pong mode, th is bit selects the initial t16_out state when timer 16 is enabled. while the timer is disabl ed, the opposite state is asserted on the pin to ensure that a tr ansition occurs when the timer is enabled. changing this bit while the counter is enabled can cause unpredictable output on t16_out. 0 1 if ctr1[3]=0, t16_out transitions from high to low when timer 16 is enabled. if ctr1[3]=0, t16_out transitions from low to high when timer 16 is enabled. demodulation mode falling edge?indicates whether a falling edge wa s detected on the i nput signal. write 1 to this flag to reset it. read 0 1 write 0 1 no falling edge detection. falling edge detection. no effect. reset flag to 0. bit position description
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 82 timer 16 control register table 38 describes the bits for the ti mer 16 control register (ctr2). table 38. counter/timer 16 control register (ctr2) bit 7 6 5 4 3 2 1 0 field t16_enable single/ modulo-n time_out t16 _clock capture_int _mask counter_int _mask p35_out reset 000 0 0 000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank d: 02h; linear: d02h bit position description [7] t16_enable?disable/enable the t16 counter. 0 1 disable t16 counter. enable t16 counter. [6] transmit mode (ctr1[7]=0) single/modulo-n?selects timer 16 terminal count action. 0 1 modulo-n mode. t16 reloads the initial value when terminal count is reached single-pass mode. t16 stops when the termi nal count is reached demodulation mode (ctr1[7]=1) enable single-edge capture. see t16 demodulation mode on page 69 . 0 1 timer 16 captures and reloads on all edges. timer 16 captures and reloads on first edge only. [5] time_out?this bit is set when th e t16 terminal count is reached. read 0 1 write 0 1 time_out?this bit is set when the t16 terminal count is reached. no counter time-out occurs. counter time-out occurred. no effect. reset flag to 0. software must reset this flag before using counter/timers. [4:3] t16 _clock?select t16 input clock frequency. these bits are not reset upon stop mode recovery . 00 01 10 11 sclk. sclk 2. sclk 4. sclk 8.
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 83 timer 8/timer 16 control register the timer 8/timer 16 counter/timer register allows the t8 and t16 counters to be syn- chronized. it also can freeze the t16 outp ut value and change t8 demodulation mode to capture one cycle of a carrier. table 39 briefly describes the bits for this bank d register. a description of each bit follows the table. [2] capture_int_mask?disable/enable interrupt when data is captured into either lo16 or hi16 upon a positive or negative edge detection in demodulation mode. this bit is not reset upon stop mode recovery. 0 1 disable data capture interrupt. enable data capture interrupt. [1] counter_int_mask?disable/enable t16 time-out interrupt. 0 1 disable t16 time -out interrupt. enable t16 time-out interrupt. [0] p35_out?select normal i/o or t8 output function for port 3, pin 5. 0 1 p35 as port output. p35 is t16 output. table 39. timer 8/timer 16 control register (ctr3) bit 7 6 5 4 3 2 1 0 field t16_enable t8_enable sync_mode t16_out disable t8 demodulate reserved reset 00 0 0 0 xxx r/w r/w r/w r/w r/w r/w ? ? ? address bank d: 03h; linear: d03h bit position value description [7] 0 1 disable t16 counter. enable t16 counter. configure t16 properly before enabling it. [6] 0 1 disable t8 counter. enable t8 counter. bit position description
ps024410-0108 p r e l i m i n a r y timers zlp12840 otp mcu product specification 84 [5] sync mode?when enabled, the first pulse of ti mer 8 (the carrier) is always synchronized with timer 16 (the demodulated signal). it can alwa ys provide a full carrier pulse. this bit is not reset upon stop mode recovery. 0 1 disable sync mode. enable sync mode. [4] t16_out disable?set this bit to disable togglin g of the timer 16 output. time-out interrupts are still generated. this bit is not reset up on stop mode recovery. 0 1 t16 toggles normally. t16 toggle is disabled. [3] t8 demodulate?(capture one cycle.) this bit is not reset upon stop mode recovery. 0 1 t8 captures events normally. t8 becomes active on the third edge, capt ures events on the fourth and fifth edges, and generates an interrupt on the fifth edge . after a t8 time-out the event count resets to 0 and the fourth and fifth edges are captured again. [2:0] reserved?always reads 111b. writes have no effect. bit position value description
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 85 interrupts the crimzon ? zlp12840 mcu features six different interrupts (see table 41 on page 87). the interrupts are maskable and prioritized (see figure 31 on page 86). the six sources are divided as follows: three sources are claimed by port 3 lines p33:p31, two by the counter/ timers and one for low-voltage detection. p32 and the uart receiver share the same interrupt. only one interrupt can be select ed as a source. when the uart receiver is enabled p32 is no longer used as an inte rrupt source. the uart transmit interrupt and uart baud rate interrupt use the same interrupt as the p33 interrupt. you must select the source that triggers the interru pt. when bit 7 of utcl is 1, the uart transmit interrupt is the source. when bit 7 of uctl is 0 and bit 5 of uctl is 1, the brg interrupt is selected. the interrupt mask register (globally or indi vidually) enables or di sables the six interrupt requests. the source for irq1 is determined by bit 1 of the port 3 mode register (p3m) and bit 4 of the smr4 register. if p3m[1]=0 (digital mo de) and smr4[4]=0, pin p33 is the irq1 source. if p3m[1]=1 (analog mode) or smr4 [4]=1 (smr interrupt enabled), the out- put of the stop mode recovery source logic is used as the source for the interrupt. see stop mode recovery interrupt on page 99. table 40. interrupt control registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no 0f9 all f9 interrupt priority register ipr xxh 90 0fa all fa interrupt request register irq 00h 92 0fb all fb interrupt mask register imr 0xxx_xxxxb 89
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 86 figure 31. interrupt block diagram uctl bits 5 & 6 = 11 irq register (bits 6 & 7) interrupt request interrupt mask register 5 vector select global interrupt enable interrupt request priority logic interrupt priority register interrupt edge select timer 16 p31 irq2 irq3 irq1 irq0 irq4 irq5 p32 uart r x p33 stop-mode recovery source uart brg interrupt uctl bits 7, 6, and 0 = 001 uart t x uctl bits 5 and 7 = 11 p3m[1] or smr4[4] timer 8 low-voltage detection 01 01 01 01
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 87 when more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the interrupt pr iority register. an interrupt machine cycle activates when an interrupt request is grante d. as a result, all subsequent interrupts are disabled, and the program counter and status flags are saved. the cy cle then branches to the program memory vector location reserved for that interrupt. all crimzon zlp12840 mcu interrupts are vectored through locati ons in the program memory. this memory location and the next byt e contain the 16-bit address of th e interrupt service routine for that particular interrupt request. to accommod ate polled interrupt syst ems, interrupt inputs are masked, and the interrupt request regist er is polled to dete rmine which of the interrupt requests require service. an interrupt resulting from an 1 is mapped into irq2, an d an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered. these interrupts are programmable. th e software can poll to identify the state of the pin. table 41. interrupt types, sources, and vectors name source vector location (program memory) comments irq0 p32, uart rx 0,1 exter nal (p32), rising, falling edge triggered irq1 p33, uart tx, brg, smr event 2,3 external (p33), falling edge triggered irq2 p31 4,5 external (p31), rising, falling edge triggered irq3 timer 16 6,7 internal irq4 timer 8 8,9 internal irq5 low-voltage detection 10,11 internal
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 88 programming bits for the interru pt edge select are located in the irq register (r250), bits d7 and bit 6. the conf iguration is indicated in table 42 . table 42. interrupt request register irq bit interrupt edge 7 6 irq2 (p31) irq0 (p32) 00f f 01f r 10r f 11r/f r/f note: f = falling edge; r = rising edge.
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 89 interrupt priority register the interrupt priority register ( table 43 ) defines which interru pts hold the highest priority. interrupts are divided into three groups of two?group a, group b, and group c. ipr bits 4, 3, and 0 determine which interrupt group has priori ty. for example, if interrupts irq5, irq1, and irq0 occur simultaneously when ipr[4:3, 0]=001b, the interrupts are serviced in the following or der: irq1, irq0, and irq5. ipr bits 5, 2, and 1 determine which interrupt within each group has higher priority. table 43. interrupt priority register (ipr) bit 7 6 5 4 3 2 1 0 field reserved group a priority group priority [2:1] group b priority group c priority group priority [0] reset xxxxxx x x r/w ?wwwww address bank independent: f9h; linear: 0f9h bit position value description [7:6] ? reserved reads are undefined; writes must be 00b. [5] 0 1 group a priority (irq3, irq5) irq5 > irq3 irq3 > irq5 {[4:3], [0]} 000 001 010 011 100 101 110 111 group priority reserved c > a > b a > b > c a > c > b b > c > a c > b > a b > a > c reserved [2] 0 1 group b priority (irq0, irq2) irq2 > irq0 irq0 > irq2 [1] 0 1 group c priority (irq1, irq4) irq1 > irq4 irq4 > irq1
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 90 interrupt request register bits 7 and 6 of the interrupt request register are used to configure the edge detection of the interrupts for port 3, bit 1 and port 3, b it 2. the remaining bits, 5 through 0, indicate the status of the interrupt. when an interrupt is serviced, the hardware automatically clears the bit to 0. writing a 1 to any of these bits ge nerates an interrupt if the appropriate bits in the interrupt mask register are enabled. wri ting a 0 to these bits clears the interrupts ( table 44 ). table 44. interrupt request register (irq) bit 7 6 5 4 3 2 1 0 field interrupt edge irq5 irq4 irq3 irq2 irq1 irq0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fah; linear: 0fah bit position value description [7:6] 00 01 10 11 interrupt edge p31 p32 p31 p32 p31 p32 p31 p32 [5] read 0 1 write 0 1 irq5 (low-voltage detection) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [4] read 0 1 write 0 1 irq4 (t8 counter) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [3] read 0 1 write 0 1 irq3 (t16 counter) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt.
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 91 the irq register is protected from change until an ei instruction is executed once. [2] read 0 1 write 0 1 irq2 (port 3 bit 1 input) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [1] read 0 1 write 0 1 irq1 (port 3 bit 3 input/smr event/uart t x /uart brg) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [0] read 0 1 write 0 1 irq0 (port 3 bit 2 input/uart r x ) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. bit position value description note:
ps024410-0108 p r e l i m i n a r y interrupts zlp12840 otp mcu product specification 92 interrupt mask register bits [5:0] are used to enable the interrupt. bit 7 is the status of the master interrupt. when reset, all interrupts are disabl ed. when writing a 1 to bit 7, you must also execute the ei instruction to enable interrupts ( table 45 ). table 45. interrupt mask register (imr) bit 7 6 5 4 3 2 1 0 field master interrupt enable reserved irq5 enable irq4 enable irq3 enable irq2 enable irq1 enable irq0 enable reset 0 x xxxxxx r/w r/w ? r/w r/w r/w r/w r/w r/w address bank independent: fbh; linear: 0fbh bit position value description [7] 0 1 master interrupt enable use only the di and ei instructions to al ter this bit. always di sable interrupts (di instruction) before wr iting this register. all interrupts are disabled. interrupts are enabled/disabled individually in bits [5:0]. [6] 0 reserved reads are undefined; writes must be 0. [5] 0 1 disables irq5. enables irq5. [4] 0 1 disables irq4. enables irq4. [3] 0 1 disables irq3. enables irq3. [2] 0 1 disables irq2. enables irq2. [1] 0 1 disables irq1. enables irq1. [0] 0 1 disables irq0. enables irq0.
ps024410-0108 p r e l i m i n a r y clock zlp12840 otp mcu product specification 93 clock the device?s on-chip oscillator has a high-gain, parallel-resonant ampl ifier, for connection to a crystal, ceramic resonator, or any suita ble external clock source (xtal1 = input, xtal2 = output). the crystal must be at cu t, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ? . the on-chip oscillator can be driven with a suitable external clock source. the crystal must be connected across xt al1 and xtal2 using the recommended capac- itors from each pin to ground. the typical capa citor value is 10 pf for 8 mhz. also check with the crystal supplier fo r the optimum capacitance. zilog ? ir mcu supports crystal, resonator, and oscillator. most resonators have a frequency tolerance of less than 0.5%, whic h is enough for remote control application. resonator has a very fast startup time, whic h is around few hundred microseconds. most crystals have a frequency tolerance of less than 50 ppm (0.005% ). however, crystal needs longer startup time than the resonator. the large loading capacitance slows down the oscillation startup time. zilog su ggests not to use more than 10 pf loading capacitor for the crystal. if the stray capacitance of th e pcb or the crystal is high, the loading capacitance c1 and c2 must be reduced furthe r to ensure stable oscillation before the t por (power-on reset time is typically 5?6 ms, see table 62 on page 132). for stop mode recovery operation, bit 5 of smr register allows you to select the stop mode recovery delay, which is the t por . if stop mode recovery delay is not selected, the mcu executes instruction immediately after it wakes up from the stop mode. if figure 32. oscillator configuration c1 c2 xtal1 xtal2 xtal1 xtal2 crystal c1, c2 = 10 pf * f=8mhz external clock *note: preliminary value. xtal1 xtal2 ceramic resonator f = 8 mhz
ps024410-0108 p r e l i m i n a r y clock zlp12840 otp mcu product specification 94 resonator or crystal is used as a clock source then stop mode recovery delay needs to be selected (bit 5 of smr = 1). for both resonator and crystal oscillator, th e oscillation ground must go directly to the ground pin of the microcontroller. the oscilla tion ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections. crystal 1 oscillator pin (xtal1) the crystal 1 oscillator time-based input pi n connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator inpu t. additionally, an op tional external single- phase clock can be connected to the on-chip oscillator input. crystal 2 oscillator pin (xtal2) the crystal 2 oscillator time-based output pin connects a parallel-re sonant, crystal, or ceramic resonant to the on-chip oscillator output. internal clock signals (sclk and tclk) the cpu and internal peripherals are driven by the internal sclk signal during normal execution. during halt mode, the interrupt logi c is driven by the internal tclk signal. these signals are produced by dividing the on-chip oscillator signal by a factor of two, and optionally by applying an additio nal divide-by-16 prescaler enabled in register bit smr[0] (see table 48 on page 102 and figure 33 ). selecting the divide-by-16 prescaler reduces device power draw during normal operation and halt mode. the prescaler is disabled by a power-on reset or stop mode recovery. figure 33. sclk/tclk circuit smr[0] 1 0 /2 /16 osc sclk tclk
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 95 resets and power management the zlp12840 provides the follo wing reduced-power modes, power monitoring, and reset features: ? power-on reset?starts the oscillator and inte rnal clock and initializes the system to its power-on reset defaults. ? voltage brownout standby?sto ps the oscillator and internal clock if a low-voltage condition occurs. initiates a power-on reset when power is restored. ? voltage detection?optionally se ts a flag if a low- or hi gh-voltage condition occurs. the low-voltage detection flag can gene rate an interrupt request, if enabled. ? halt mode?stops the internal clock to the cpu until an enabled interrupt request is received. ? stop mode?stops the clock an d oscillator, reducing the mcu supply current to a very low level until a power-on reset or stop mode recovery occurs. ? stop mode recovery?restarts the oscillator and internal clock and initializes most of the system to its power-on reset defaults. some register values are not reset by a stop mode recovery. ? watchdog timer?optionally generates a po wer-on reset if the program fails to execute the wdt instruction with in a specified time interval. for supply current values under various conditions, see dc characteristics on page 129 . figure 34 on page 96 displays the power-on reset sources. table 46 lists control registers for reset and power management features. some features are affected by registers described in other chapters. table 46. reset and power management registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no d0c d 0c low-voltage detection register lvd 1111_1000b 98 f0a f 0a stop mode recovery register 4 smr4 x x x 0 _ 0 0 0 0b 111 f0b f 0b stop mode recovery register smr 0 0 1 0_ 0 0 00 b 102 note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 96 f0c f 0c stop mode recovery register 1 smr1 00h 105 f0d f 0d stop mode recovery register 2 smr2 x 0 x 0 _ 0 0 x xb 107 f0e f 0e stop mode recovery register 3 smr3 x0h 110 f0f f 0f watchdog timer mode register wdtmr x x x x _ 1 1 0 1b 112 figure 34. resets and watchdog timer table 46. reset and power management registers (continued) address (hex) reset 12-bit bank 8-bit register description mnemonic page no 18-clock reset generator reset clr2* wdt tap select clk clr1 por/wdt 1 234 low operating voltage detection internal reset active high xtal v dd vbo from stop-mode recovery source wdt smr[5] 0 1 12 ns glitch filter + 5-clock filter wdt/por counter chain *clr1 and clr2 enable the wdt/por and 18 clock reset timers, respectively, upon a low-to-high input translation. v cc internal rc oscillator reset
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 97 power-on reset timer when power is initially applie d to the device, a timer circuit clocked by a dedicated on- board rc-oscillator provides the power-on reset timer function. the por timer circuit is a one-shot timer that keeps the internal reset signal asserted long enough for v dd and the oscillator circuit to stabilize before instruction execution begins. the reset timer is triggered by one of three conditions: ? initial power-on or recovery from a voltage brownout/standby condition. ? stop mode recovery (if register bit smr[5] = 1) ? watchdog timer time-out. smr[5] can be cleared to 0 to bypass the po r timer upon a stop mode recovery. this should only be done when using an external clock that does not require a start-up delay. reset/stop mode recovery status read-only bit smr[7]=0 if the previous reset was initiated by a power-on reset (including brown-out or wdt resets). smr[7]=1 if the pr evious reset was initiated by a stop mode recovery. a power-on, brown-out, or wdt reset restor es all registers to their power-on reset defaults. a stop mode recovery restores most registers to their power-on reset defaults. register bits not reset by a stop mode recove ry are highlighted in grey in the register tables. register bit smr[7] is set to 1 in stead of reset by a stop mode recovery. voltage brownout/standby an on-chip voltage comparator checks that the v dd is at the required level for correct operation of the device. reset is globally driven when v dd falls below v bo . a small drop in v dd causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. if the v dd is allowed to stay above v ram , the ram content is preserved. when the power level is returned to above v bo , the device performs a power-on reset and functions normally. voltage detection the voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) offers an option of monitoring the v cc voltage. the voltage detec tion is enabled when bit 0 of lvd register is set. after vo ltage detection is enabled, the v cc level is monitored in
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 98 real time. the hvd flag (bit 2 of the lvd register) is set only if v cc is higher than v hvd. the lvd flag (bit 1 of the lvd register) is set only if v cc is lower than the v lvd . when voltage detection is en abled, the lvd flag also triggers irq5. the irq bit 5 latches the low voltage condition until it is cl eared by instructions or reset. the irq5 interrupt is served if it is enabled in the im r register. otherwise, bit 5 of irq register is latched as a flag only. do not modify register p01m while checkin g a low-voltage condition. switching noise coming from port 0 can trigger the lvd flag. voltage detection does not work in stop mode. this register is described in table 47 . halt mode this instruction turns off the internal cpu clock, but not the xt al oscillation. the counter/timers, uart, and interrupts irq0, irq1, irq2, irq3, irq4, and irq5 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (enabl ed) to exit halt mode. after the interrupt service routine, the program continues from the instruction after halt mode. to enter halt mode, first flush the instructi on pipeline to avoid susp ending execution in mid-instruction. execute a nop (op code = ffh ) immediately before the appropriate sleep instruction, as follows: table 47. low-voltage detection register (lvd) bit 7 6 5 4 3 2 1 0 field reserved high battery detect low battery detect voltage detect enable reset 11111 0 0 0 r/w rrrrr r r r/w address bank d: 0ch; linear: d0ch bit position r/w value description [7:3] ? ? reserved?reads 11111b. writes have no effect. [2] r0 1 hvd clear. high voltage detected. v cc >v hvd [1] r0 1 lvd clear. low voltage detected. v cc >v lvd [0] r/w 0 1 voltage detection disabled. voltage detection enabled. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 99 ff nop ; clear the pipeline 7f halt ; enter halt mode power consumption during halt mode can be reduced by first setting smr[0]=1 to enable the divide-by-16 clock prescaler. stop mode this instruction turns off the internal clock and external c rystal oscillation, reducing the mcu supply current to a ve ry low level. for stop mode current specifications, see dc characteristics on page 129 . to enter stop mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. execute a nop (op code = ffh ) immediately before the appropriate sleep instruction, as follows: ff nop ; clear the pipeline 6f stop ; enter stop mode stop mode is terminated only by a reset, su ch as wdt time-out, por, or one of the smr events described in the follo wing sections. this condition ca uses the processor to restart the application program at address 000ch . unlike a normal por or wdt reset, a smr reset does not reset the contents of some reg- isters and bits. register bits not reset by a smr are highlighted in grey in the register tables. register bit smr[7] is set to 1 by a smr. fast stop mode recovery smr[5] can be cleared to 0 before entering stop mode to bypass the default t por reset timer upon smr. see power-on reset timer on page 97. if smr[5]=0, the smr source must be kept active for at leas t 10 input clock periods (tpc). smr[5] must be set to 1 if using a c rystal or resonator clock source. the t por delay allows the clock source to stab ilize before executing instructions. stop mode recovery interrupt software can set register bit smr4[4] = 1 to en able routing of smr events to irq1 and to port 3, pin 3. in this configuration, if an ir q1 interrupt occurs, regi ster bit p3[3] = 0 indi- cates that a smr event is occurring. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 100 stop mode recovery event sources any port 2 or 3 input pin can be configured to generate a smr event, either individually or in a variety of logical combinations. the partname provides the following registers for smr source configuration and status: ? smr register?selects one port 3, pin 1?3 pin state or one of three port 2 pin logical combinations to generate an event when a defined 0 or 1 level occurs. ? smr1 register?configure one or more port 2 input pins (0?7)to la tch the latest read or write value and generate an event when the pin state changes. ? smr2 register?selects one of seven port 2 and 3 pin logical combinations to gener- ate an event when a defi ned 0 or 1 level occurs. ? smr3 register?configure one or more port 3 input pins (0?3 ) to latch the latest read or write value and generate an event when the pin state changes. ? smr4 register?enables routing of smr even ts to irq1. indicates whether port data has been latched for smr1 or smr3 event monitoring, and whether the latch was on a port read or write. a smr event occurs if any of the sources defined in the smr, smr1, smr2, and smr3 registers is active. smr register events the smr register function is similar to the standard smr feature used in previous z8 cpu-compatible parts. register bits smr[4:2] are set to select one of six event modes, as displayed in figure 35 on page 101. the output of the corresponding logic is compared to the state of smr[6]; when they are the same, a smr event is generated. if smr[4:2]=000, no event source is selected by smr. the state smr[4:2]=001 is reserved and selects no event in this device. the logic configured by the smr register ignor es any port pins that are configured as an output, or that are selected as source pins in registers smr1 or smr3. the smr register is summarized in table 48 on page 102.
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 101 figure 35. smr register-controlled event sources v p31 p32 p33 p3m[1] or p27 p20 0 1 p23 p20 p27 smr[4:2] = 000 smr[4:2] = 010 smr[4:2] = 011 smr[4:2] = 100 smr[4:2] = 101 smr4[4] sm[4:2] = 110 sm[4:2] = 111 smr[6] smr3 smr2 smr1 smr to reset and wdt circuitry (active low) to irq1 and p0[3] cc the smr register logic ignores any pin configured as an output in the p2m or p3m registers or as a source in the smr1 or smr3 registers.
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 102 [ table 48. stop mode recovery register (smr) bit 7 6 5 4 3 2 1 0 field stop flag stop mode recovery level stop delay stop mode recovery source reserved sclk/tclk divide-by-16 reset 0 0 1 0 0 00 0 r/w rw wwwww w address bank f: 0bh; linear: f0bh bit position value description [7] 0 1 stop flag?indicates whether last startup was power-on reset or stop mode recovery. a write to this bit has no effect. power-on reset. stop mode recovery. [6] 0 1 stop mode recovery level?sele cts whether an smr[4:2]-s elected smr is initiated by a low or high level at the xor-gate input (see figure 35 on page 101). low. high. [5] 0 1 stop delay?controls the reset delay after recovery. must be 1 if using a crystal or resonator clock source. off. on. [4:2] 000 001 010 011 100 101 110 111 stop mode recovery source?specifies a stop mode recovery wake-up source at the xor gate input (see figure 35 on page 101). this value is not changed by a stop mode recovery. the following equations ignore any port pin configured as output or selected in smr1 or smr3. no smr register source selected. reserved. p31. p32. p33. p27. port 2 nor 0?3. port 2 nor 0?7. [1] ? reserved?reads are undefined; must write 0. [0] 0 1 sclk/tclk divide-by-16 select?controls a divide-by-16 prescaler of the internal sclk/tclk signal (see internal clock signals (sclk and tclk) on page 94). a power-on reset or stop mode re covery clears this bit to 0. off. on.
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 103 smr1 register events the smr1 register can be used to configure one or more port 2 pins to be to be compared to a written or sampled reference value and ge nerate a smr event when the pin state dif- fers from the reference value. to configure a port 2 pin as an smr1 event so urce, make sure it is configured as an input in the p2m register, then set the correspondi ng smr1 register bit. by default, a smr event occurs when the pin?s state is zero. after a port 2 pin is configured as an smr1 source, any subsequent read from or write to the p2 register latches the re ad or written value for refere nce. a smr event occurs when the pin?s state differs from the last reference value latched. the smr1 source logic is dis- played in figure 36 on page 104. the program can read register bits smr4[1:0] to determine wh ether the port 2 pins trigger a smr on a change from the last read value (s mr4[1:0]=01), or on a change from the last written value (smr4[1:0]=10). software can clea r smr4[1:0] to 00 to restore the default behavior (configured pins trigger when their state is 0). the smr1 register is summarized in table 49 on page 105. after the following example code is executed, a 1 on p2 0 will wake the part from stop mode. after the following example code is executed wh en the value of p2 is 00h, a 1 on p20 will wake the part from stop mode: ld p2m, #%ff ;set port 2 to inputs. srp #%0f ;point to expanded bank f ld smr1, #%01 ;select p20 for smr1. srp #%00 ;point to bank 0 ld p2, #%00 ;write 00h to port 2, so the p20 reference ;value is 0, and a 1 on p20 wakes the part. nop stop ld p2m, #%ff ;set ports to inputs. srp #%0f ;point to expanded bank f ld smr1, #%01 ;select p20 for smr1. srp #%00 ;point to bank 0 ld r6, p2 ;if a 0 is read from port 2, the p20 reference ;value is 0, so a 1 on p20 wakes the part. nop stop
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 104 figure 36. smr1 register-controlled event sources p3m[1] or p33 0 1 port 2, pin n individual port 2 pin smr logic, n = 0-7 bit p2m[ n ] bit smr1[ n ] bit p2[ n ] smr4[4] smr3 smr2 to reset and wdt circuitry (active low) to smr1 smr smr1 dq p20 logic p21 logic p22 logic p23 logic p24 logic p25 logic p26 logic p27 logic port 2 read/write irq1 register p3, bit 3
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 105 this register is not reset after a smr. table 49. stop mode recovery register 1 (smr1) bit 7 6 5 4 3 2 1 0 field p27 stop select p26 stop select p25 stop select p24 stop select p23 stop select p22 stop select p21 stop select p20 stop select reset 0 0 0 0 0 0 0 0 r/w wwwwwwww address bank f: 0ch; linear: f0ch bit position value description [7] 0 1 p27 not selected. p27 selected as an smr source. [6] 0 1 p26 not selected. p26 selected as an smr source. [5] 0 1 p25 not selected. p25 selected as an smr source. [4] 0 1 p24 not selected. p24 selected as an smr source. [3] 0 1 p23 not selected. p23 selected as an smr source. [2] 0 1 p22 not selected. p22 selected as an smr source. [1] 0 1 p21 not selected. p21 selected as an smr source. [0] 0 1 p20 not selected. p20 selected as an smr source. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 106 smr2 register events the smr2 register function is similar to the standard smr feature used in previous z8 cpu-compatible parts. regist er bits smr2[4:2] are set to select one of seven event modes, as displayed in figure 37 . the output of the correspon ding logic is compared to the state of smr2[6]; when they are the same, a smr event is generated. if smr2[4:2]=000, no event source is selected by smr2. the logic configured by the smr2 register igno res any port pins that are configured as an output, or that are selected as source pins in registers smr1 or smr3. the smr2 register is summarized in table 50 on page 107. figure 37. smr2 register-controlled event sources p00 p32 smr2[4:2] = 000 smr2[4:2] = 010 smr2[4:2] = 011 smr2[4:2] = 100 smr2[4:2] = 101 smr2[4:2] = 110 smr2[4:2] = 111 smr2[4:2] = 001 p20 p32 p23 p20 p27 p31 p33 p31 p33 p32 p31 p33 p00 p07 p32 p31 p33 p07 p20 p32 p31 p33 p21 p22 smr2[6] v cc p3m[1] or 0 1 smr4[4] p33 to reset and wdt circuitry (active low) to irq1 and p0[3] smr3 smr2 smr1 smr the smr2 register logic ignores any pin configured as an output in the p2m or p3m registers or as a source in the smr1 or smr3 registers.
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 107 this register is not reset after a smr. smr3 register events the smr3 register can be used to configure one or more of port 3, pins 0?3 to be compared to a written or sampled reference va lue and generate a smr event when the pin state differs from the reference value. table 50. stop mode recovery register 2 (smr2) bit 7 6 5 4 3 2 1 0 field reserved stop mode recovery level 2 reserved stop mode recovery source reserved reset x 0 x 0 0 0 x x r/w ? w ? www ? address bank f: 0dh; linear: f0dh bit position value description [7] ? reserved?read is undefined; write must be 0. [6] 0 1 stop mode recovery level 2 selects whether an smr2 [4:2]-selected smr is initiated by a low or high level at the xor-gate input (see figure 37 on page 106). low. high. [5] ? reserved?read is undefined; write must be 0. [4:2] 000 001 010 011 100 101 110 111 stop mode recovery source specifies a smr wake-up source at the xor gate input (see figure 37 on page 106). additional sources can be selected by smr, smr1, and smr3 registers. if more than one source is selected, any selected source event causes a smr . the following equations ignore any port pin that is selected in register smr1 or configured as an output. no smr2 register source selected. nand of p23:p20. nand of p27:p20. nor of p33:p31. nand of p33:p31. nor of p33:p3 1, p00, p07. nand of p33:p31, p00, p07. nand of p33:p31, p22:p20. [1:0] ? reserved?read is undefined; write must be 00b. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 108 to configure a port 3 input pin as an smr3 event source set the co rresponding smr3 reg- ister bit. by default, a smr event oc curs when the pin?s state is zero. after a port 3 pin is configured as an smr3 source, any subsequent read from or write to the p2 register latches the re ad or written value for refere nce. a smr event occurs when the pin?s state differs from the last reference value latched. the smr3 source logic is dis- played in figure 38 on page 109. the program can read register bits smr4[3:2] to determine wh ether the port 3 pins trigger a smr on a change from the last read value (s mr4[3:2]=01), or on a change from the last written value (smr4[3:2]=10). software can clea r smr4[3:2] to 00 to restore the default behavior (configured pins trigger when their state is 0). the smr3 register is summarized in table 48 on page 102. after the following example co de is executed, a 1 on p30 will wake the part from stop mode. after the following example code is executed wh en the value of p3 is 00h, a 1 on p30 will wake the part from stop mode. ld smr3, #%01 ;select p30 from smr3. ld p3, #%00 ;write 00h to port 3, so the p30 reference ;value is 0, and a 1 on p30 wakes the part. nop stop ld smr3, #%01 ;select p30 for smr3. ld r6, p3 ;if a 0 is read from port 3, the p30 reference ;value is 0, so a 1 on p30 wakes the part. nop stop
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 109 figure 38. smr3 register-controlled event sources p3m[1] or p33 0 1 port 3, pin n p ort 3 read/write individual port 3 pin smr logic, n = 0-3 bit smr3[ n ] bit p3[ n ] smr4[4] smr3 smr2 to reset and wdt circuitry (active low ) to irq1 and p0[3] to smr 3 smr smr1 dq p30 logic p31 logic p32 logic p33 logic
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 110 this register is not reset after a smr. table 51. stop mode recovery register 3 (smr3) bit 7 6 5 4 3 2 1 0 field ?p33 smr select p32 smr select p31 smr select p30 smr select reset x x x x 0 0 0 0 r/w ???? wwww address bank f: 0eh; linear: f0eh bit position value description [7:4] ? reserved?reads undefined; writes have no effect. [3] 0 1 p33 not selected. p33 smr source selected. [2] 0 1 p32 not selected. p32 smr source selected. [1] 0 1 p31 not selected. p31 smr source selected. [0] 0 1 p30 not selected. p30 smr source selected. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 111 stop mode recovery register 4 the stop mode recovery register 4 (smr4) register enables the smr interrupt source and indicates the reference value st atus for registers smr1 and smr3. this register is not reset after a smr. table 52. stop mode recovery register 4 (smr4) bit 7 6 5 4 3 2 1 0 field reserved smr irq enable port 3 smr status port 2 smr status reset x x x 0 0 0 0 0 r/w ? ? ? r/w r/w r/w r/w r/w address bank f: 0ah; linear: f0ah bit position value description [7:5] ? reserved?reads are undefined; must write 000b. [4] 0 1 smr irq enable if p3m[1]=0, smr events do not generate an interrupt. smr events generate an interrupt on irq1. [3:2] 00 01 10 11 port 3 smr status no read or write of the p3 register occurs. p3 read occurs; used as smr3 reference. p3 write occurs; used as smr3 reference. reserved. [1:0] 00 01 10 11 port 2 smr status no read or write of the p2 register occurs. p2 read occurs; use p2 read as smr1 reference. p2 write occurs; use p2 write as smr1 reference. reserved. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 112 watchdog timer the watchdog timer is a retr iggerable one-shot timer that resets the z8 lxm cpu if it reaches its terminal count. the wdt must initially be enabled by executing the wdt instruction. on subsequent ex ecutions of the wdt instructio n, the wdt is refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source is the internal rc-oscilla tor. bits 0 and 1 of the wdt register con- trol a tap circuit that determines the minimu m time-out period. bit 2 determines whether the wdt is active during halt, and bit 3 determines wdt activity during stop mode. bits 4 through 7 are reserved (see table 53 ). this register is accessible only during the first 60 processor cycles (120 xtal clocks ) from the execution of the first instruction after power-on reset, watchdog timer reset, or a smr (see stop mode on page 99). after this point, the register cannot be modi fied by any means (intentional or otherwise). the wdtmr register cannot be read. the regist er is located in bank f of the expanded register group at address location 0fh . this register is not reset after a smr. table 53. watchdog timer mode register (wdtmr) bit 7 6 5 4 3 2 1 0 field ? wdt during stop mode wdt during halt mode time-out select reset x x x x 1 1 0 1 r/w xxxx w w w w address bank f: 0fh; linear: f0fh bit position value description [7:4] ? reserved?reads are undefined; must write 0000. [3] 0 1 wdt during stop mode? determines whether or not the wdt is active during stop mode. off. wdt active during stop mode. [2] 0 1 wdt during halt mode? determines whether the wdt is active or not during halt mode. see figure 34 on page 96 . off. wdt active during halt mode. note:
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 113 [1:0] 00 01 10 11 time-out select?selects the wdt time period. 5 ms minimum. 10 ms minimum. 20 ms minimum. 80 ms minimum. bit position value description
ps024410-0108 p r e l i m i n a r y resets and power management zlp12840 otp mcu product specification 114
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 115 z8 lxm cpu programming summary this chapter provides informa tion for programming the z8 lxm cpu included in this device. for details on the cpu an d its instruction set, refer to z8 lxm cpu core user manual (um0183) . addressing notation table 54 summarizes z8 lxm cpu addressing mo des and symbolic notation. the text variable n represents a decimal number; aa represents a hexadecimal address; and label represents a label defined elsewhere in the assembly source. in reference notation only , lowercase is used to distingui sh 4-bit addressed working regis- ters (r1, r2) from 8-bit addressed registers (r1, r2). the numerals 1 and 2, respectively, indicate whether the register is used for destination or source addressing. . table 54. symbolic notation for operands symbol assembly operand description cc ? condition code cc represents a condition code mnemonic. see condition codes on page 119. im # n immediate data im represents an immediate data value, prefixed by # in assembly language. the immediate value follows the instruction opcode in program memory. n = 0 to 255. r1 r2 r n working register r1 or r2 represents the name, r n , of a working register, where n = 0, 1, 2,..., 15. the equivalent 12-bit addre ss is {rp[3:0], rp[7:4], n }. rr1 rr2 rr n working register pair rr1 or rr2 represents the name, r n , of a working register pair, where n = 0, 2, 4,..., 14. the equivalent 12-bit address is {rp[3:0], rp[7:4], n }. r1 r2 % aa register r1 or r2 represents an 8-bit register address. for addresses 00h?dfh or f0h?ffh, the equivalent 12-bit address is {rp[3:0], % aa }. for addresses e0h?efh (escaped mode), the equivalent 12-bit address is {rp[3:0], rp[7:4], % aa [3:0]}. rr1 rr2 % aa register pair (8-bit address) rr1 or rr2 represents the 8-bit address of a register pair. for addresses 00h?dfh or f0h?ffh, the equivalent 12-bit address is {rp[3:0], % aa }. for addresses e0h?efh (escaped mode), the equivalent 12-bit address is {rp[3:0], rp[7:4], % aa [3:0]}.
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 116 irr1 irr2 @r n indirect working register ir1 or ir2 represents the name a working register, r n, where n = 0, 1, 2,..., 15. @ indicates indirect working register add ressing using an 8-bit effective address contained in the specified wo rking register. the accessed register?s equivalent 12-bit address is {rp[3:0], 8-bit effective address }. irr1 irr2 @rr n indirect working register pair irr1 or irr2 represents the name a working register pair, rr n, where n = 0, 2, 4,..., 14. @ indicates indirect working register addressing using an effective address in the specified working register pair. depending on the instruction, the effective address is in the register file (12-bit address) or program/constant memory (16-bit address). ir1 ir2 @% aa indirect register ir1 or ir2 represents the 8-bit address of a register. @ indicates indirect register addressing using an 8-bit effective address contained in the specified register. the accessed r egister?s equivalent 12-bit address is {rp[3:0], 8-bit effective address }. irr1 @% aa indirect register pair irr1 represents the 8-bit address of a register. @ indicates indirect register addressing wit h a 16-bit effective address (in program memory) contained in the specified register pair. x(r1) x(r2) % aa (r n ) indexed (x) addressing x represents the 8-bit base address to which the offset is added. r1 or r2 represents the name, r n , of a working register containing the 8-bit signed offset. the 8-bit effective address is the sum of x and the contents of working register r n . the accessed register?s eq uivalent 12-bit address is {rp[3:0], 8-bit effective address }. da label direct address (jp, call) in a jp or call operand, da is a 16-bit program memory address in the range of 0000h to ffffh . da replaces the contents of the program counter to cause execution to continue at a new location in program memory. in assembly source, the address is typically represented as a label. ra label relative address (jr, djnz) ra is a signed 8-bit program memory offset in the range +127 to -128, relative to the address of the next instruction in program me mory. in a jr or djnz operation, ra is added to the program counter to cause execution to continue at a new location in program memory. in assembly source, the jump address is typically represented as an absolute label, and the assembler calculates ra. table 54. symbolic notation for operands (continued) symbol assembly operand description
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 117 table 55 consists of additional symbols that are used throughout the instruction set summary. table 55. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix c carry flag sp stack pointer value pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix assignment of a value. for example, dst dst + src indicates the result is st ored in the destination. ? exchange of two values ~ one?s complement unary operator
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 118 flags register the flags register provides inform ation on the current status of the z8 cpu. it consists of six bits of status information ( table 56 ). table 56. flags register (flags) bit 7 6 5 4 3 2 1 0 field c z s o d h f1 f2 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fch; linear 0fch bit position value description [7] 0 1 carry flag (c) set when the result of an ar ithmetic operation generates a carry out of or a borrow into the high-order bit (bit 7) of the result. al so used in rotate and shift instructions. flag clear flag set [6] 0 1 zero flag (z) set when the result of an arithmetic operation is 0. flag clear flag set [5] 0 1 sign flag (s) stores the value of the most significant bit following an arithmetic , logical, rotate, or shift instruction. flag clear flag set [4] 0 1 overflow flag (o) set when the result of an arithmetic operation is greater than 127. flag clear flag set [3] 0 1 decimal adjust flag (d) used for binary-coded decimal (bcd) arithmetic. flag clear flag set [2] 0 1 half carry flag (h) set when a carry out of or borrow into bit 3 of an arithmetic operation occurs. flag clear flag set
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 119 condition codes the c, z, s and v flags control the operati on of the conditional jump (jp cc and jr cc) instructions. sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc). table 57 summarizes the co ndition codes. some binary condition codes can be created using more than one assembl y code mnemonic. the result of the flag test operation determ ines if the conditional jump executes. [1] 0 1 user flag 1 (f1) available to software for use as a general-purpose bit. bit clear bit set [0] 0 1 user flag 2 (f2) available to software for use as a general-purpose bit. bit clear bit set table 57. condition codes binary hex assembly mnemonic definition flag test operation 0000 0 f always false ? 0001 1 lt less than (s xor v) = 1 0010 2 le less than or equal (z or (s xor v)) = 1 0011 3 ule unsigned less than or equal (c or z) = 1 0100 4 ov overflow v = 1 0101 5 ml minus s = 1 0110 6 z zero z = 1 0110 6 eq equal z = 1 0111 7 c carry c = 1 0111 7 ult unsigned less than c = 1 1000 8 t (or blank) always true ? 1001 9 ge greater than or equal (s xor v) = 0 1010 a gt greater than (z or (s xor v)) = 0 bit position value description
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 120 z8 lxm cpu instruction summary table 58 summarizes the z8 lxm cpu instructions . the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. 1011 b ugt unsigned greater than (c = 0 and z = 0) 1100 c nov no overflow v = 0 1101 d pl plus s = 0 1110 e nz non-zero z = 0 1110 e ne not equal z = 0 1111 f nc no carry c = 0 1111 f uge unsigned greater than or equal c = 0 table 58. z8 lxm cpu instruction summary assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute adc dst, src dst dst + src + c r r 12 * * * * 0 * 6 5 rir 13 6 5 r r 14 10 5 rir 15 10 5 rim 16 10 5 ir im 17 10 5 table 57. condition codes (continued) binary hex assembly mnemonic definition flag test operation
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 121 add dst, src dst dst + src r r 02 * * * * 0 * 6 5 rir 03 6 5 r r 04 10 5 rir 05 10 5 rim 06 10 5 ir im 07 10 5 and dst, src dst dst and src r r 52 ? * * 0 ? ? 6 5 rir 53 6 5 r r 54 10 5 rir 55 10 5 rim 56 10 5 ir im 57 10 5 call dst sp sp -2 @sp pc pc dst irr d4 ?????? 20 0 da d6 20 0 ccf c ~c ef *????? 6 5 clr dst dst 00h r b0 ?????? 6 5 ir b1 6 5 com dst dst ~dst r 60 ? * * 0 ? ? 6 5 ir 61 6 5 cp dst, src dst ? src ? c r r a2 * * * * ? ? 6 5 rir a3 6 5 rr a4 10 5 rir a5 10 5 rim a6 10 5 ir im a7 10 5 da dst dst da(dst) r 40 * * * x ? ? 8 5 ir 41 8 5 table 58. z8 lxm cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 122 dec dst dst dst ? 1 r 00 ? * * * ? ? 6 5 ir 01 6 5 decw dst dst dst ? 1 rr 80 ? * * * ? ? 10 5 ir 81 10 5 di disable interrupts irqctl[7] 0 8f ?????? 6 1 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a?fa ?????? nz/z 12/10 5 ei enable interrupts irqctl[7] 1 9f ?????? 6 1 halt halt mode 7f ?????? 7 0 inc dst dst dst + 1 r 20 ? * * * ? ? 6 5 ir 21 6 5 r0e?fe 65 incw dst dst dst + 1 rr a0 ? * * * ? ? 10 5 ir a1 10 5 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ****** 16 0 jp dst pc dst da 8d ?????? 12 0 irr 30 8 0 jp cc, dst if cc is true pc dst da 0d?fd ? ? ? ? ? ? t/f 12/10 0 jr dst pc pc + x ra 8b ?????? 12 0 jr cc, dst if cc is true pc pc + x ra 0b?fb ? ? ? ? ? ? t/f 12/10 0 table 58. z8 lxm cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 123 ld dst, src dst src r im 0c?fc ? ? ? ? ? ? 6 5 r r 08?f8 6 5 r r 09?f9 6 5 rx(r) c7 10 5 x(r) r d7 10 5 rir e3 6 5 rr e4 10 5 rir e5 10 5 rim e6 10 5 ir im e7 10 5 ir r f3 6 5 ir r f5 10 5 ldc dst, src dst src r irr c2 ?????? 12 0 irr r d2 12 0 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 ? ? ? ? ? ? 18 0 irr ir d3 18 0 ldx dst, src dst src r irr 82 ?????? 12 0 irr r 92 12 0 ldxi dst, src dst src r r + 1 rr rr + 1 ir irr 83 ? ? ? ? ? ? 18 0 irr ir 93 18 0 nop no operation ff ? ? ? ? ? ? 6 0 or dst, src dst dst or src r r 42 ? * * 0 ? ? 6 5 rir 43 6 5 r r 44 10 5 rir 45 10 5 rim 46 10 5 ir im 47 10 5 table 58. z8 lxm cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 124 pop dst dst @sp sp sp + 1 r 50 ?????? 10 5 ir 51 10 5 push src sp sp ? 1 @sp src r 70 ?????? 10 1 ir 71 12 1 rcf c 0 cf 0????? 6 5 ret pc @sp sp sp + 2 af ?????? 14 0 rl dst r 90 ****?? 6 5 ir 91 6 5 rlc dst r 10 * * * * ? ? 6 5 ir 11 6 5 rr dst r e0 ****?? 6 5 ir e1 6 5 rrc dst r c0 * * * * ? ? 6 5 ir c1 6 5 sbc dst, src dst dst ? src ? c r r 32 * * * * 1 * 6 5 rir 33 6 5 r r 34 10 5 rir 35 10 5 rim 36 10 5 ir im 37 10 5 scf c 1 df 1????? 6 5 sra dst r d0 * * * 0 ? ? 6 5 ir d1 6 5 table 58. z8 lxm cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 125 srp src rp src im 31 ?????? 6 1 stop stop mode 6f ?????? 6 0 sub dst, src dst dst ? src r r 22 * * * * 1 * 6 5 rir 23 6 5 r r 24 10 5 rir 25 10 5 rim 26 10 5 ir im 27 10 5 swap dst dst[7:4] ? dst[3:0] r f0 ? * * x ? ? 8 5 ir f1 8 5 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 6 5 rir 63 6 5 r r 64 10 5 rir 65 10 5 rim 66 10 5 ir im 67 10 5 tm dst, src dst and src r r 72 ? * * 0 ? ? 6 5 rir 73 6 5 r r 74 10 5 rir 75 10 5 rim 76 10 5 ir im 77 10 5 wdt 5f ?????? 6 0 table 58. z8 lxm cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute
ps024410-0108 p r e l i m i n a r y z8 lxm cpu programming summary zlp12840 otp mcu product specification 126 xor dst, src dst dst xor src r r b2 ? * * 0 ? ? 6 5 rir b3 6 5 rr b4 10 5 rir b5 10 5 rim b6 10 5 ir im b7 10 5 flag states: * = state depends on result; ? = no change; x = undefined; 0 = cleared; 1 = set table 58. z8 lxm cpu instruction summary (continued) assembly mnemonic symbolic operation address mode op- code(s) (hex) flags cycles dst src c z s v d h fetch execute
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 127 electrical characteristics absolute maximum ratings stresses greater than those listed in table 59 may cause permanent damage to the device. these ratings are stress ratings only. functiona l operation of the device at any condition outside those indicated in the op erational sections of these sp ecifications is not implied. exposure to absolute maximu m rating conditions for extended periods may affect device reliability. for improved reliability, unused in puts should be tied to one of the supply voltages (v dd or v ss ). table 59. absolute maximum ratings parameter minimum maximum units ambient temperature under bias 0 +70 c storage temperature ?65 +150 c voltage on any pin with respect to v ss *?0.3+5.5v voltage on v dd pin with respect to v ss ?0.3 +3.6 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma maximum current into v dd or out of v ss 75 ma *this voltage applies to all pins except v dd , p32, and p33.
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 128 standard test conditions the characteristics listed in th is product specification apply for standard test conditions as noted. all voltages are referenced to ground. positive current flows into the referenced pin (see figure 39 ). capacitance table 60 lists the capacitances. figure 39. test load diagram table 60. capacitance parameter maximum input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd. from output under test 150 pf i
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 129 dc characteristics table 61 describes the direct current char acteristics of the zlp12840 otp mcu. table 61. dc characteristics symbol parameter v cc t a = 0 o c to +70 o c units conditions minimum typ maximum v cc supply voltage 1 2.0 3.6 v see notes 5 v ch clock input high voltage 2.0?3.6 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0?3.6 v ss ?0.3 0.4 v driven by external clock generator v ih input high voltage 2.0?3.6 0.7 v cc v cc +0.3 v v il input low voltage 2.0?3.6 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0?3.6 v cc ?0.4 v i oh = ?0.5 ma v oh2 output high voltage (p36, p37, p00, p01) 2.0?3.6 v cc ?0.8 v i oh = ?7 ma v ol1 output low voltage 2.0?3.6 0.4 v i ol = 4.0 ma v ol2 output low voltage (p00, p01, p36, p37) 2.0?3.6 0.8 v i ol = 10 ma v offset comparator input offset voltage 2.0?3.6 25 mv v ref comparator reference voltage 2.0?3.6 0 v dd ?1.75 v i il input leakage 2.0?3.6 ?1 1 a v in = 0 v, v cc; pull-ups disabled. i il1 input leakage ir amp (p31) 2.0?3.6 ?2.5 ?12 a v in = 0 v, ir amp enabled. i ol output leakage 2.0?3.6 ?1 1 ma v in = 0 v, v cc i cc supply current 2,3 2.0 1 3 ma at 8.0 mhz 3.6 5 10 ma at 8.0 mhz i cc1 standby current 2,3 (halt mode) 2.0 0.5 1.6 ma v in = 0 v, v cc at 8.0 mhz 3.6 0.8 2.0 ma
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 130 i cc2 standby current 4 (stop mode) 2.0 1.6 8 a v in = 0 v, v cc wdt is not running 3.6 1.8 10 a 2.0 5 20 a v in = 0 v, v cc wdt is running 3.6 8 30 a i lv standby current 5 (low voltage) 1.2 6 a measured at 1.3 v v bo v cc low-voltage protection 1.9 2.0 v 8 mhz maximum external clock frequency v lvd v cc low-voltage detection 2.4 v v hvd v cc high-voltage detection 2.7 v t oniramp wake-up time from disabled mode 2.0?3.6 20 s i det ir amp current for signal detection 2.0?3.6 10 100 a ir amp enabled notes 1. zilog ? recommends adding a filter capacitor (minimum 0.1 f), physically close to v dd and v ss if operating voltage fluctuations are anticipa ted, such as those resulting from driving an infrared led. 2. all outputs unloaded, inputs at rail. 3. cl1 = cl2 = 100 pf. 4. oscillator stopped. 5. oscillator stops when v cc falls below v bo limit. table 61. dc characteristics (continued) symbol parameter v cc t a = 0 o c to +70 o c units conditions minimum typ maximum
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 131 ac characteristics figure 40 and table 62 on page 132 describe the altern ating current (ac) characteristics. figure 40. ac timing diagram clock 1 3 4 8 2 2 3 t in irq n 6 5 7 7 11 clock setup 9 stop-mode recovery source 10
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 132 table 62. ac characteristics sl no symbol parameter v cc t a = 0 o c to +70 o c 8.0 mhz units wdtmr (bits 1:0) minimum maximum 1t p c input clock period 1 2.0?3.6 121 dc ns 2t r c,t f c clock input rise and fall times 1 2.0?3.6 25 ns 3t w c input clock width 1 2.0?3.6 37 ns 4t w t in l timer input low width 1 2.0 100 ns 3.6 70 ns 5t w t in h timer input high width 1 2.0?3.6 3t p c 6t p t in timer input period 1 2.0?3.6 8t p c 7t r t in ,t f t in timer input rise and fall timers 1 2.0?3.6 100 ns 8t w il interrupt request low time 1,2 2.0 100 ns 3.6 70 ns 9t w ih interrupt request input high time 1,2 2.0?3.6 5t p c 10 t wsm stop mode recovery width spec 2.0?3.6 12 3 10 t p c 4 ns 11 t ost oscillator start-up time 4 2.0?3.6 5t p c 12 t wdt watchdog timer delay time 2.0?3.6 5 ms 0, 0 2.0?3.6 10 ms 0, 1 2.0?3.6 20 ms 1, 0 2.0?3.6 80 ms 1, 1 13 t por power-on reset 2.0?3.6 2.5 10 ms
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 133 14 f max maximum frequency of input signal for ir amplifier 500 khz 15 f min minimum frequency of input signal for ir amplifier 0khz notes 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33:p31). 3. smr ? bit 5 = 1. 4. smr ? bit 5 = 0. table 62. ac characteristics (continued) sl no symbol parameter v cc t a = 0 o c to +70 o c 8.0 mhz units wdtmr (bits 1:0) minimum maximum
ps024410-0108 p r e l i m i n a r y electrical characteristics zlp12840 otp mcu product specification 134
ps024410-0108 p r e l i m i n a r y packaging zlp12840 otp mcu product specification 135 packaging figure 41 displays the 28-pin shrink small ou tline package (ssop) for the zlp12840 device. figure 41. 28-pin ssop package diagram symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a'
ps024410-0108 p r e l i m i n a r y packaging zlp12840 otp mcu product specification 136 figure 42 displays the 28-pin small outline inte grated circuit (soic) package for the zlp12840 device. figure 42. 28-pin soic package diagram
ps024410-0108 p r e l i m i n a r y packaging zlp12840 otp mcu product specification 137 figure 43 displays the 28-pin plastic dual inline package (pdip) for the zlp12840 device. figure 43. 28-pin pdip package diagram
ps024410-0108 p r e l i m i n a r y packaging zlp12840 otp mcu product specification 138 figure 44 displays the 20-pin shrink small ou tline package (ssop) for the zlp12840 device. figure 44. 20-pin ssop package diagram
ps024410-0108 p r e l i m i n a r y packaging zlp12840 otp mcu product specification 139 figure 45 displays the 20-pin small outline inte grated circuit (soic) package for the zlp12840 device. figure 45. 20-pin soic package diagram
ps024410-0108 p r e l i m i n a r y packaging zlp12840 otp mcu product specification 140 figure 46 displays the 20-pin plastic dual inline package (pdip) for the zlp12840 device. figure 46. 20-pin pdip package diagram
ps024410-0108 p r e l i m i n a r y ordering information zlp12840 otp mcu product specification 141 ordering information table 63 provides a product specification index code and a brief description of each part. each of the parts listed in table 63 is shown in a lead-free package. the use of lead-free packaging adheres to a so cially responsible environmental standard. for a description of a part number?s un ique identifying attributes, see the part number description on page 142. applications an d support tools the following developm ent tools are available for pr ogramming and debugging this device: ? zcrmznice01zemg?crimzon in-circuit emulator ? zcrmznice01zacg?20-pin accessory kit to the zcrmznice01zemg ? zcrmznice02zacg?40-/48 -pin accessory kit to the zcrmznice01zemg table 63. zlp12840 otp mcu part numbers description psi no description psi no description lead-free environmental flow zlp12840h2828g 28-pin ssop 128k ot p zlp12840h2896g 28-pin ssop 96k otp zlp12840s2828g 28-pin soic 128k otp zlp12840s2896g 28-pin soic 96k otp zlp12840p2828g 28-pin pdip 128k otp zlp12840p2896g 28-pin pdip 96k otp zlp12840h2028g 20-pin ssop 128k otp zlp12840h2096g 20-pin ssop 96k otp zlp12840s2028g 20-pin soic 128k otp zlp12840s2096g 20-pin soic 96k otp zlp12840p2028g 20-pin pdip 128k otp zlp12840p2096g 20-pin pdip 96k otp zlp12840h2864g 28-pin ssop 64k otp zlp12840h2832g 28-pin ssop 32k otp zlp12840s2864g 28-pin soic 64k otp zlp12840s2832g 28-pin soic 32k otp ZLP12840P2864G 28-pin pdip 64k otp zlp12840p2832g 28-pin pdip 32k otp zlp12840h2064g 20-pin ssop 64k otp zlp12840h2032g 20-pin ssop 32k otp zlp12840s2064g 20-pin soic 64k otp zlp12840s2032g 20-pin soic 32k otp zlp12840p2064g 20-pin pdip 64k otp zlp12840p2032g 20-pin pdip 32k otp
ps024410-0108 p r e l i m i n a r y ordering information zlp12840 otp mcu product specification 142 ? zcrmzn00100kitg?crimzon ir development kit ? zilog developer studio ii (zdsii) , available for download at www.zilog.com for valuable informa tion about customer and technical support as well as hardware and software development tools, visit the zilog web site at www.zilog.com . the latest released version of zds can be down loaded from this web site. part number description zilog ? part numbers consist of a number of components, as displayed in figure 47 . the example part number zlp12840h2828g is a crimzon one-time programmable (otp) product in a 28-pin ssop packag e, with 128 kb of otp and built with lead-free solder. figure 47. part number example zlp12840h2828g environmental flow g = lead free memory size 28 = 128 kb otp 96 = 96 kb otp 64 = 64 kb otp 32 = 32 kb otp number of pins in package 20 = 20 pins 28 = 28 pins package type h = ssop s = soic p = pdip product number: 12840 product line: crimzon otp zilog product prefix
ps024410-0108 p r e l i m i n a r y ordering information zlp12840 otp mcu product specification 143 precharacterization product the product represented by this document is newly introduced and zilog ? has not com- pleted the full characterization of the prod uct. the document states what zilog knows about this product at this time, but additi onal features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery might be uncertain at times due to start-up yield issues. for more information, visit www.zilog.com .
ps024410-0108 p r e l i m i n a r y ordering information zlp12840 otp mcu product specification 144
zlp12840 otp mcu product specification ps024410-0108 p r e l i m i n a r y index 145 index numerics 12-bit address map 33 16-bit counter/t imer circuits 68 20-pin package pins 5, 7 pdip package 140 soic package 139 ssop package 138 28-pin package pins 8, 9, 10 pdip package 137 soic package 136 ssop package 135 8-bit counter/timer circuits 63 a absolute maximum ratings 127 ac characteristics 131, 132 ac timing 131 active low notation 3 address 12-bit linear 33 notation 115 amplifier, infrared 43 and caution 77 architecture mpu 1 uart 45 asynchronous data 47 b baud rate generator description 52 example 53 interrupt 52 baud rate generator constant register (bcnst) 57 block diagram counter/timer 59 interrupt 86 mcu 3 reset and watchdog timer 96 uart 46 brown-out, voltage 97 c capacitance 128 caution open-drain output 11 stopping timer 64 timer count 63 timer modes 78 timer registers 69 uart transmit 48 characteristics ac 131, 132 dc 129 electrical 127 clock 93 internal signals 94 cmos gate, caution 11 comparator inputs 19 outputs 19 condition codes 119 conditions, test 128 connection, power 3 constant memory 27, 28 constant, baud rate 57 counter/timer block diagram 59 capture flowchart 65 output configuration 18 crystal 93 crystal oscillator pins (xtal1, xtal2) 94
zlp12840 otp mcu product specification ps024410-0108 p r e l i m i n a r y index 146 d data format, uart 46, 47 data handling, uart 51 dc characteristics 129 demodulation changing mode 78 flowchart 65, 66 timer 64, 69 demodulation mode flowchart 67 device architecture 1 block diagram 3 features 1 part numbers 141 diagram, package 135, 136, 137, 138, 139, 140 divisor, baud rate 57 e electrical characteristics 127 error handling, uart 51 example bcnst register 53 register pointer 31 f fast recovery, stop mode 99 features, device 1 feedback form 151 flags register 118 floating cmos gate, caution 11 flowchart demodulation mode 65, 66, 67 timer transmit 62 uart receive 52 form, feedback 151 format, uart data 46, 47 functional bl ock diagram 3 functions, i/o port pins 11 h h suffix 63 halt mode 98 handshaking, uart 50 i i/o port pin functions 11 infrared learning amplifier 43 input comparator 19 timers 60 instruction set summary 120 instruction symbols 117 internal clock 94 interrupt baud rate generator 52 block diagram 86 description 85 mask register 92 priority register 89 request register 88, 90 source 87 stop mode recovery 99 type 87 uart 50 uart receive 49, 50, 52 uart transmit 48, 50 vector 87 interrupt mask register (imr) 92 interrupt priority register (ipr) 89 interrupt request register (irq) 88, 90 l lde and ldei inst ructions removed 33 ldx, ldxi instruction addresses 33 leakage, caution 11 learning amplifier, infrared 43 linear address 32 load, test 128 low-voltage detection register (lvd) 98
zlp12840 otp mcu product specification ps024410-0108 p r e l i m i n a r y index 147 m map program/constant memory 28 register 12-bit 33 register 8-bit 30 register file summary 39 maximum ratings 127 mcu block diagram 3 features 1 part numbers 141 memory address, linear 32 program/constant 27 program/constant map 28 register 12-bit map 33 register file map 30 register file summary 39 modulo-n mode 64, 69 mpu architecture 1 n notation addressing 115 operand 115 o open-drain output caution 11 operand symbols 115 operation, uart 46 or caution 77 ordering information 141 oscillator 93 otp memory 27 output comparator 19 timer/counter 71 timer/counter circuit 72 timer/counter configuration 18 overline, in text 3 overrun, uart 51 p package diagram 135, 136, 137, 138, 139, 140 package information 135 parity, uart data 47 part number format 141, 142 pin description 5 pin function port 0 12 port 2 13 port 3 14 port 3 summary 17 ping-pong mode 70, 71 pins 20-pin package 5, 7 28-pin package 8, 9, 10 polled uart receive 49 polled uart transmit 47 port 0 configuration 13 pin function 12 port 0 mode register (p01m) 20 port 0 register (p0) 21 port 2 configuration 14 pin function 13 port 2 mode register (p2m) 22 port 2 register (p2) 23 port 3 configuration 15 counter/timer output 18 pin function 14 pin function 17 port 3 mode register (p3m) 24 port 3 register (p3) 25 port configuration register (pcon) 19, 20 port pin functions 11 power connection 3 power management 95 power-on reset timer 97 precharacterization 143 program memory description 27 map 28 program memory paging register (pmpr) 33, 34
zlp12840 otp mcu product specification ps024410-0108 p r e l i m i n a r y index 148 programming summary 115 pull-up, disabled 11 r ratings, maximum 127 register bcnst 57 ctr1 79 ctr3 83 hi16 74 hi8 73 imr 92 ipr 89 irq 88, 90 lo16 74 lo8 73 lvd 98 p0 21 p01m 20 p2 23 p2m 22 p3 25 p3m 24 pcon 19, 20 pmpr 33, 34 rp 35 smr 102 smr1 105 smr2 107 smr3 110 smr4 111 spl 36, 37 uctl 56 urdata 54 user 36 ust 55 utdata 54 wdtmr 112 register file 12-bit address 33 address summary 39 description 28 memory map 30 register pointer detail 31 example 31 register pointe r register (rp) 35 register pointer register (rp) 35 reset block diagram 96 delay bypass 99 features 95 por timer 97 status 97 timer terminal count 76 s sclk signal 94 single-pass mode 64, 69 source interrupt 87 stop mode recovery 100, 101, 104, 106, 109 stack 29 stack pointer re gister (spl) 36, 37 standard test conditions 128 standby, brown-out 97 status reset 97 uart 55 stop bit, uart 51 stop mode description 99 fast recovery 99 recovery events 100, 106, 107 recovery interrupt 99 recovery source 100, 101, 104, 106, 109 recovery status 97 stop mode recovery register (smr) 102 stop mode recovery register 1 (smr1) 105 stop mode recovery register 2 (smr2) 107 stop mode recovery register 3 (smr3) 110 stop mode recovery register 4 (smr4) 111 stop-mode recovery events 100, 103 stop mode recovery register 4 (smr4) 111 suffix, h 63
zlp12840 otp mcu product specification ps024410-0108 p r e l i m i n a r y index 149 symbols address 115 instruction 117 operand 115 t t16_out signal modulo-n mode 69 single-pass mode 69 t8_out signal modulo-n mode 64 single-pass mode 64 tclk signal 94 terminal count, reset 76 test conditions 128 test load 128 timer block diagram 59 changing mode 78 description 59 input circuit 60 output circuit 72 output configuration 18 output description 71 reset 97 starting count caution 63 stopping caution 64 t16 demodulation 69 t16 transmit 68 t16_out signal 69 t8 demodulation 64 t8 transmit 61 t8_out signal 64 transmit flowchart 62 transmit versus demodulation mode 78 timer 16 capture high register (hi16) 74 timer 16 capture low register (l016) 74 timer 16 control register (ctr2) 82 timer 16 high hold register (tc16h) 74, 75 timer 16 low hold register (tc16l) 75 timer 8 and timer 16 co mmon functions register (ctr1) 79 timer 8 capture high register (hi8) 73 timer 8 capture low register (l08) 73 timer 8 control register (ctr0) 76, 77 timer 8 high hold register (tc8h) 75, 76 timer 8 low hold register (tc8l) 76 timer 8/timer 16 control register (ctr3) 83 timing, ac 131 transmit caution, uart 48 transmit mode caution 78 flowchart 62 timer 61, 68 u uart architecture 45 baud rate generator 52 block diagram 46 data and error handling 51 data format 46, 47 interrupts 50 operation 46 overrun error 51 polled receive 49 polled transmit 47 receive interrupt 49, 50, 52 stop bit 51 transmit caution 48 transmit interrupt 48, 50 uart control register (uctl) 56 uart receive/transmit data register (urdata/ utdata) 54 uart status register (ust) 55 user data register (user) 36 v vector, interrupt 87 voltage brown-out 97 detection 97 detection register 98
zlp12840 otp mcu product specification ps024410-0108 p r e l i m i n a r y index 150 w watchdog timer description 112 diagram 96 watchdog timer mode register (wdtmr) 112 x xtal1 pin 94 xtal2 pin 94 z zlp12840 mcu block diagram 3 features 1 part numbers 141
ps024410-0108 p r e l i m i n a r y customer support zlp12840 otp mcu product specification 151 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at h ttp://www.zilog.com/kb . for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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